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| single-chip 5-port 10/100mbps switch controller with dual mii interfaces datasheet rev. 1.2 02 march 2005 track id: jatr-1076-21 RTL8305SC www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller ii track id: jatr-1076-21 rev. 1.2 copyright ?2005 realtek semiconductor corp. all rights reserv ed. no part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of realtek semiconductor corp. trademarks realtek is a trademark of realtek semiconductor cor poration. other names mentioned in this document are trademarks/registered trademarks of their respective owners. disclaimer realtek provides this document ?as is?, without wa rranty of any kind, neith er expressed nor implied, including, but not limited t o, the particular purpose. realtek may make improvements and/or changes in this document or in the product described in this document at any time. this document could include technical inaccuracies or typographical errors. using this document this document is intended for use by the software engineer when programming for realtek RTL8305SC controller chips. information pertaining to the hardwa re design of products using these chips is contained in a separate document. though every effort has been made to assure that this document is cu rrent and accurate, more information may have become available subsequent to the producti on of this guide. in that event, please contact your realtek representative for additional information that may help in the development process. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller iii track id: jatr-1076-21 rev. 1.2 revision history revision release date summary 1.0 2004/06/17 first release. removed qos function ipv6 differentiated services and removed table 147, page 113. 1.1 2004/06/30 revised ledmode[1:0]=00, in table 4, page 14, table 7, page 20, table 19, page 30, and table 69, page 59. changed four combinations of led mode to three combinations of led display mode, page 3. corrected section 7.3.10 phy 2 register 23: ?port 2 control register 1? to ?global option 1 register?, page 71. revised pull low resister to 1k ohm, table 5, page 16. revised phy register in table 64, page 55. changed table 139?s name from phy 0 to phy 5, page 87. changed table 140?s name from phy 8 to phy 5, page 88. add p4phy_mode select, in table 143, page 103. corrected pin52 mtxen/prxdv/en_t runk to mtxen/prxdv, pin92 led_act[4]/disfcautooff to led_act[4], and pin115 enagback/led_dup[0] to led_dup[0], in figure 2, page 7, and table 1, page 8. canceled the description of pin92 led_act[4]/disfcautooff and pin115 enagback/led_dup[0], section 1, page 2, in table 9, page 22, and section 8.3.10, page 123. reserved phy 0 register 18.7 and 18.15, in table 68, page 58. reserved eeprom register 4.7, in table 16, page 28 and register 5.7, table 17, page 29. corrected qos based features, section 2, page 4. corrected 2sb1188k to 2sb1188 and hvdd18 to dvdd18, in figure 24, page 132, and table 151, page 132. corrected ?24lc02 must be 1. 8vcompatible? to ?24lc02 must be 3.3vcompatible?, section 8.3.3, page 117. corrected ttl input high voltage 1.5v to 2.0v and ttl input low voltage 1.0v to 0.8v, section 9.3, page 134. corrected phy 4 register 18 description, in table 124, page 81. 1.2 2005/03/02 add 100base-tx td and rd differential output impedance (return loss) columns and delete 10base-tx td and rd differential output impedance (return loss) columns, in section 9.4 ac characteristics, page 135. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller iv track id: jatr-1076-21 rev. 1.2 table of contents 1. general description............................................................................................................ ....................................1 2. features....................................................................................................................... ....................................................4 3. block diagram.................................................................................................................. ...........................................6 4. pin assignments ................................................................................................................ ...........................................7 5. pin descriptions ............................................................................................................... ...........................................9 5.1. m edia c onnection p ins ............................................................................................................................... .............9 5.2. p ort 4 c onfiguration p ins ............................................................................................................................... .......9 5.3. p ort 4 mac c ircuit i nterface p ins .....................................................................................................................14 5.4. p ort 4 phy c ircuit i nterface p ins ......................................................................................................................16 5.5. m iscellaneous p ins ............................................................................................................................... ................19 5.6. p ort led p ins ............................................................................................................................... ..........................20 5.7. s erial eeprom and smi p ins ..............................................................................................................................2 2 5.8. s trapping p ins ............................................................................................................................... ..........................22 5.9. p ort s tatus s trapping p ins ............................................................................................................................... ....24 5.10. p ower p ins ............................................................................................................................... ................................26 6. eeprom desc ription............................................................................................................. ...................................27 6.1. p ort 0 r egisters ............................................................................................................................... ......................27 6.1.1. global contro l register0 ....................................................................................................... ..............................27 6.1.2. global contro l register1 ....................................................................................................... ..............................27 6.1.3. global contro l register2 ....................................................................................................... ..............................28 6.1.4. global contro l register3 ....................................................................................................... ..............................28 6.1.5. global contro l register4 ....................................................................................................... ..............................28 6.1.6. global contro l register5 ....................................................................................................... ..............................29 6.1.7. global contro l register6 ....................................................................................................... ..............................29 6.1.8. global contro l register7 ....................................................................................................... ..............................30 6.1.9. port 0 control 0............................................................................................................... .....................................30 6.1.10. port 0 control 1............................................................................................................... .....................................31 6.1.11. port 0 control 2............................................................................................................... .....................................31 6.1.12. port 0 control 3............................................................................................................... .....................................31 6.1.13. port 0 control 4 & vlan entry [a].............................................................................................. .......................32 6.2. p ort 1 r egisters ............................................................................................................................... ......................33 6.2.1. internal use register.......................................................................................................... ..................................33 6.2.2. port 1 control 0............................................................................................................... .....................................33 6.2.3. port 1 control 1............................................................................................................... .....................................34 6.2.4. port 1 control 2............................................................................................................... .....................................34 6.2.5. port 1 control 3............................................................................................................... .....................................34 6.2.6. port 1 control 4 & vlan entry [b].............................................................................................. .......................35 6.3. p ort 2 r egisters ............................................................................................................................... ......................36 6.3.1. internal use register.......................................................................................................... ..................................36 6.3.2. port 2 control 0............................................................................................................... .....................................36 6.3.3. port 2 control 1............................................................................................................... .....................................37 6.3.4. reserved ....................................................................................................................... ........................................37 6.3.5. port 2 control 2 & vlan entry [c] .............................................................................................. ......................38 6.4. p ort 3 r egisters ............................................................................................................................... ......................39 6.4.1. switch mac address ............................................................................................................. ...............................39 6.4.2. port 3 control 0............................................................................................................... .....................................39 6.4.3. port 3 control 1............................................................................................................... .....................................40 6.4.4. reserved ....................................................................................................................... ........................................40 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller v track id: jatr-1076-21 rev. 1.2 6.4.5. port 3 control 2 & vlan entry [d] .............................................................................................. ......................40 6.4.6. internal use register.......................................................................................................... ..................................41 6.5. p ort 4 r egisters ............................................................................................................................... ......................42 6.5.1. port 4 control 0............................................................................................................... .....................................42 6.5.2. port 4 control 1............................................................................................................... .....................................42 6.5.3. reserved ....................................................................................................................... ........................................43 6.5.4. port 4 control 2 & vlan entry [e].............................................................................................. .......................43 6.5.5. internal use register.......................................................................................................... ..................................44 6.5.6. 802.1p base priority........................................................................................................... ..................................44 6.6. vlan e ntries ............................................................................................................................... ..........................44 6.6.1. vlan entry [f]................................................................................................................. ...................................44 6.6.2. vlan entry [g] ................................................................................................................. ..................................45 6.6.3. vlan entry [h] ................................................................................................................. ..................................45 6.6.4. vlan entry [i] ................................................................................................................. ....................................46 6.6.5. vlan entry [j] ................................................................................................................. ...................................46 6.6.6. vlan entry [k]................................................................................................................. ...................................47 6.6.7. vlan entry [l] ................................................................................................................. ...................................47 6.6.8. vlan entry [m] ................................................................................................................. ..................................48 6.6.9. vlan entry [n]................................................................................................................. ...................................48 6.6.10. vlan entry [o] ................................................................................................................. ..................................49 6.6.11. vlan entry [p]................................................................................................................. ...................................49 7. register descriptions .......................................................................................................... ................................50 7.1. phy 0 r egisters ............................................................................................................................... ......................53 7.1.1. phy 0 register 0 for port 0: control ........................................................................................... ........................53 7.1.2. phy 0 register 1 fo r port 0: status............................................................................................ ..........................54 7.1.3. phy 0 register 2 for po rt 0: phy identifie r 1 .................................................................................. ...................54 7.1.4. phy 0 register 3 for po rt 0: phy identifie r 2 .................................................................................. ...................55 7.1.5. phy 0 register 4 for port 0: auto-negotiation advertisem ent .................................................................... ........55 7.1.6. phy 0 register 5 for port 0: au to-negotiation link partner ability ............................................................. ......56 7.1.7. phy 0 register 16: global control 0............................................................................................ .......................56 7.1.8. phy 0 register 17: global control 1............................................................................................ .......................58 7.1.9. phy 0 register 18: global control 2............................................................................................ .......................58 7.1.10. phy 0 register 19: global control 3............................................................................................ .......................59 7.1.11. phy 0 register 22: port 0 control re gister 0................................................................................... ...................60 7.1.12. phy 0 register 24: port 0 control regi ster 1 & vlan id [a] membership ......................................................61 7.1.13. phy 0 register 25: port 0 contro l register 2 & vlan id [a] ..................................................................... ......61 7.1.14. phy 0 register 26: reserved or vlan id [f] membership.......................................................................... ......62 7.1.15. phy 0 register 27: reserv ed or vlan id [f]..................................................................................... ................62 7.1.16. phy 0 register 28: reserved or vlan id [k] membership.......................................................................... ......63 7.1.17. phy 0 register 29: reserv ed or vlan id [k] ..................................................................................... ...............63 7.1.18. phy 0 register 30: reserved or vlan id [p] membership.......................................................................... ......64 7.1.19. phy 0 register 31: reserv ed or vlan id [p]..................................................................................... ................64 7.2. phy 1 r egisters ............................................................................................................................... ......................65 7.2.1. phy 1 register 0 for port 1: control ........................................................................................... ........................65 7.2.2. phy 1 register 1 fo r port 1: status............................................................................................ ..........................65 7.2.3. phy 1 register 2 for po rt 1: phy identifie r 1 .................................................................................. ...................65 7.2.4. phy 1 register 3 for po rt 1: phy identifie r 2 .................................................................................. ...................65 7.2.5. phy 1 register 4 for port 1: auto-negotiation advertisem ent .................................................................... ........65 7.2.6. phy 1 register 5 for port 1: au to-negotiation link partner ability ............................................................. ......65 7.2.7. phy 1 register 16~17: internal use register.................................................................................... ..................65 7.2.8. phy 1 register 18~19: internal use register.................................................................................... ..................65 7.2.9. phy 1 register 22: port 1 control re gister 0................................................................................... ...................66 7.2.10. phy 1 register 23: glob al option re gister 0.................................................................................... ..................66 7.2.11. phy 1 register 24: port 1 control regi ster 1 & vlan id [b] membership ......................................................66 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller vi track id: jatr-1076-21 rev. 1.2 7.2.12. phy 1 register 25: port 1 contro l register 2 & vlan id [b] ..................................................................... ......67 7.2.13. phy 1 register 26: reserved or vlan id [g] membership .......................................................................... .....67 7.2.14. phy 1 register 27: reserv ed or vlan id [g] ..................................................................................... ...............68 7.2.15. phy 1 register 28: reserved or vlan id [l] membership .......................................................................... ......68 7.2.16. phy 1 register 29: reserv ed or vlan id [l]..................................................................................... ................69 7.3. phy 2 r egisters ............................................................................................................................... ......................70 7.3.1. phy 2 register 0 for port 2: control ........................................................................................... ........................70 7.3.2. phy 2 register 1 fo r port 2: status............................................................................................ ..........................70 7.3.3. phy 2 register 2 for po rt 2: phy identifie r 1 .................................................................................. ...................70 7.3.4. phy 2 register 3 for po rt 2: phy identifie r 2 .................................................................................. ...................70 7.3.5. phy 2 register 4 for port 2: auto-negotiation advertisem ent .................................................................... ........70 7.3.6. phy 2 register 5 for port 2: au to-negotiation link partner ability ............................................................. ......70 7.3.7. phy 2 register 16~17: internal use register.................................................................................... ..................70 7.3.8. phy 2 register 18~19: internal use register.................................................................................... ..................70 7.3.9. phy 2 register 22: port 2 control re gister 0................................................................................... ...................71 7.3.10. phy 2 register 23: glob al option 1 register.................................................................................... ..................71 7.3.11. phy 2 register 24: port 2 control regi ster 2 & vlan id [c] membership ......................................................71 7.3.12. phy 2 register 25: port 2 contro l register 3 & vlan id [c] ..................................................................... ......72 7.3.13. phy 2 register 26: reserved or vlan id [h] membership .......................................................................... .....72 7.3.14. phy 2 register 27: reserv ed or vlan id [h] ..................................................................................... ...............73 7.3.15. phy 2 register 28: reserved or vlan id [m] membership .......................................................................... .....73 7.3.16. phy 2 register 29: reserv ed or vlan id [m]..................................................................................... ...............74 7.4. phy 3 r egisters ............................................................................................................................... ......................75 7.4.1. phy 3 register 0 for port 3: control ........................................................................................... ........................75 7.4.2. phy 3 register 1 fo r port 3: status............................................................................................ ..........................75 7.4.3. phy 3 register 2 for po rt 3: phy identifie r 1 .................................................................................. ...................75 7.4.4. phy 3 register 3 for po rt 3: phy identifie r 2 .................................................................................. ...................75 7.4.5. phy 3 register 4 for port 3: auto-negotiation advertisem ent .................................................................... ........75 7.4.6. phy 3 register 5 for port 3: au to-negotiation link partner ability ............................................................. ......75 7.4.7. phy 3 register 16~18: switch mac address ....................................................................................... ...............75 7.4.8. phy 3 register 19~21: internal use register.................................................................................... ..................76 7.4.9. phy 3 register 22: port 3 control re gister 0................................................................................... ...................76 7.4.10. phy 3 register 24: port 3 control regi ster 1 & vlan id [d] membership ......................................................76 7.4.11. phy 3 register 25: port 3 contro l register 2 & vlan id [d]..................................................................... ......77 7.4.12. phy 3 register 26: reserved or vlan id [i] membership.......................................................................... .......77 7.4.13. phy 3 register 27: reserv ed or vlan id [i]..................................................................................... .................78 7.4.14. phy 3 register 28: reserved or vlan id [n] membership.......................................................................... ......78 7.4.15. phy 3 register 29: reserv ed or vlan id [n] ..................................................................................... ...............79 7.5. phy 4 r egisters ............................................................................................................................... ......................80 7.5.1. phy 4 register 0 for port 4: control ........................................................................................... ........................80 7.5.2. phy 4 register 1 fo r port 4: status............................................................................................ ..........................80 7.5.3. phy 4 register 2 for po rt 4: phy identifie r 1 .................................................................................. ...................80 7.5.4. phy 4 register 3 for po rt 4: phy identifie r 2 .................................................................................. ...................80 7.5.5. phy 4 register 4 for port 4: auto-negotiation advertisem ent .................................................................... ........80 7.5.6. phy 4 register 5 for port 4: au to-negotiation link partner ability ............................................................. ......80 7.5.7. phy 4 register 16: indi rect access control..................................................................................... ....................80 7.5.8. phy 4 register 17~20: indirect access data..................................................................................... ..................81 7.5.9. phy 4 register 21: 802 .1p base priority........................................................................................ .....................81 7.5.10. phy 4 register 22: port 4 control re gister 0................................................................................... ...................82 7.5.11. phy 4 register 24: port 4 control regi ster 1 & vlan id [e] membership ......................................................82 7.5.12. phy 4 register 25: port 4 contro l register 2 & vlan id [e] ..................................................................... ......83 7.5.13. phy 4 register 26: reserved or vlan id [j] membership .......................................................................... ......83 7.5.14. phy 4 register 27: reserv ed or vlan id [j] ..................................................................................... ................84 7.5.15. phy 4 register 28: reserved or vlan id [o] membership .......................................................................... .....84 7.5.16. phy 4 register 29: reserv ed or vlan id [o] ..................................................................................... ...............85 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller vii track id: jatr-1076-21 rev. 1.2 7.6. phy 5 r egisters ............................................................................................................................... ......................86 7.6.1. phy 5 register 0 for po rt 4 mac: control....................................................................................... ...................86 7.6.2. phy 5 register 1 for port 4 mac: status ........................................................................................ ....................87 7.6.3. phy 5 register 2 for port 4 mac: phy identifie r 1.............................................................................. ..............87 7.6.4. phy 5 register 3 for port 4 mac: phy identifie r 2.............................................................................. ..............87 7.6.5. phy 5 register 4 for port 4 mac: auto-negotiation advertisement................................................................ ...88 7.6.6. mii port nw ay mode ............................................................................................................. ..............................89 7.6.7. mii port fo rce mode ............................................................................................................ ...............................89 8. functional description......................................................................................................... ..............................90 8.1. s witch c ore f unctional o verview .....................................................................................................................90 8.1.1. applica tions................................................................................................................... .......................................90 8.1.2. port 4......................................................................................................................... ...........................................90 8.1.3. port status co nfigura tion...................................................................................................... ...............................94 8.1.4. flow control ................................................................................................................... .....................................95 8.1.5. address search, learning, and aging ............................................................................................ ......................97 8.1.6. address direct mapping mode.................................................................................................... .........................97 8.1.7. half duplex op eration .......................................................................................................... ...............................98 8.1.8. interframe gap................................................................................................................. ...................................98 8.1.9. illegal frame.................................................................................................................. ......................................98 8.1.10. dual mii interface............................................................................................................. ...................................99 8.2. p hysical l ayer f unctional o verview ..............................................................................................................110 8.2.1. auto-negotiatio n for utp ....................................................................................................... ........................... 110 8.2.2. 10base-t trans mit func tion ..................................................................................................... ......................... 110 8.2.3. 10base-t rece ive func tion ...................................................................................................... .......................... 111 8.2.4. link monitor................................................................................................................... .................................... 111 8.2.5. 100base-tx transmit function................................................................................................... ....................... 111 8.2.6. 100base-tx r eceive func tion.................................................................................................... ........................ 111 8.2.7. 100base-fx ..................................................................................................................... ................................... 111 8.2.8. 100base-fx transmit function................................................................................................... ....................... 112 8.2.9. 100base-fx recei ve function .................................................................................................... ....................... 112 8.2.10. 100base-fx fefi ................................................................................................................ .............................. 112 8.2.11. reduced fiber interface ........................................................................................................ ............................. 113 8.2.12. power savi ng mode.............................................................................................................. .............................. 113 8.2.13. reg0.11 power- down mode........................................................................................................ ....................... 114 8.2.14. crossover detection an d auto correction........................................................................................ .................. 114 8.2.15. polarity detecti on and correction .............................................................................................. ....................... 114 8.3. a dvanced f unctional o verview .......................................................................................................................115 8.3.1. reset .......................................................................................................................... ......................................... 115 8.3.2. setup and con figuration........................................................................................................ ............................. 116 8.3.3. serial eeprom ex ample: 24lc02.................................................................................................. .................. 117 8.3.4. smi ............................................................................................................................ ......................................... 119 8.3.5. head-of-line blocki ng .......................................................................................................... ............................ 119 8.3.6. port-based vlan ................................................................................................................ ............................... 119 8.3.7. ieee 802.1q tagged-vid based vlan.............................................................................................. ...............121 8.3.8. port vid (pvid)................................................................................................................ .................................122 8.3.9. lookup tabl e access............................................................................................................ ...............................123 8.3.10. qos func tion................................................................................................................... ...................................123 8.3.11. insert/remove vlan tag......................................................................................................... ...........................125 8.3.12. filtering/forwarding rese rved control frame .................................................................................... .............125 8.3.13. broadcast stor m control ........................................................................................................ ............................126 8.3.14. broadcast in /out drop .......................................................................................................... .............................126 8.3.15. loop det ection ................................................................................................................. ..................................127 8.3.16. mac local loopback re turn to external .......................................................................................... ................128 8.3.17. reg.0.14 phy digital loo pback return to internal............................................................................... ............129 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller viii track id: jatr-1076-21 rev. 1.2 8.3.18. leds........................................................................................................................... ........................................129 8.3.19. 1.8v power generation .......................................................................................................... ............................132 8.3.20. crystal/osc illator ............................................................................................................. ..................................132 9. characteristics ................................................................................................................ .....................................133 9.1. a bsolute m aximum r at i n g s ............................................................................................................................... 133 9.2. o perating r ange ............................................................................................................................... ...................133 9.3. dc c haracteristics ............................................................................................................................... ..............134 9.4. ac c haracteristics ............................................................................................................................... ..............135 9.5. d igital t iming c haracteristics .........................................................................................................................136 9.6. t hermal c haracteristics ............................................................................................................................... ....139 9.6.1. package description ............................................................................................................ ..............................139 9.6.2. pcb descri ption................................................................................................................ .................................139 9.6.3. assembly material .............................................................................................................. ................................139 9.6.4. simulation analys is conditions................................................................................................. .........................140 9.6.5. results ........................................................................................................................ ........................................140 10. application information ........................................................................................................ ......................141 10.1. utp (10b ase -t/100b ase -tx) a pplication .........................................................................................................141 10.2. 100b ase -fx a pplication ............................................................................................................................... .......143 11. design and layout guide........................................................................................................ ........................145 12. mechanical dimensions .......................................................................................................... .......................147 12.1. m echanical d imensions n otes ..........................................................................................................................148 13. ordering information........................................................................................................... .........................148 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller ix track id: jatr-1076-21 rev. 1.2 list of tables t able 1. p in a ssignments ............................................................................................................................... ...........................8 t able 2. m edia c onnection p ins ............................................................................................................................... ..............9 t able 3. p ort 4 c onfiguration p in d efinitions .....................................................................................................................9 t able 4. p ort 4 mac c ircuit i nterface p in d efinitions ...................................................................................................14 t able 5. p ort 4 phy c ircuit i nterface p in d efinitions .....................................................................................................16 t able 6. m iscellaneous p ins ............................................................................................................................... ..................19 t able 7. p ort led p ins ............................................................................................................................... ............................20 t able 8. s erial eeprom and smi p ins ............................................................................................................................... .22 t able 9. s trapping p ins ............................................................................................................................... ............................22 t able 10. p ort s tatus s trapping p ins ............................................................................................................................... ......24 t able 11. p ower p ins ............................................................................................................................... ..................................26 t able 12. g lobal c ontrol r egister 0 .............................................................................................................................. ......27 t able 13. g lobal c ontrol r egister 1 .............................................................................................................................. ......27 t able 14. g lobal c ontrol r egister 2 .............................................................................................................................. ......28 t able 15. g lobal c ontrol r egister 3 .............................................................................................................................. ......28 t able 16. g lobal c ontrol r egister 4 .............................................................................................................................. ......28 t able 17. g lobal c ontrol r egister 5 .............................................................................................................................. ......29 t able 18. g lobal c ontrol r egister 6 .............................................................................................................................. ......29 t able 19. g lobal c ontrol r egister 7.............................................................................................................................. ......30 t able 20. p ort 0 c ontrol 0 .............................................................................................................................. ........................30 t able 21. p ort 0 c ontrol 1 .............................................................................................................................. ........................31 t able 22. p ort 0 c ontrol 2 .............................................................................................................................. ........................31 t able 23. p ort 0 c ontrol 3 .............................................................................................................................. ........................31 t able 24. p ort 0 c ontrol 4 & vlan e ntry [a] ....................................................................................................................32 t able 25. i nternal u se r egister ............................................................................................................................... ..............33 t able 26. p ort 1 c ontrol 0 .............................................................................................................................. ........................33 t able 27. p ort 1 c ontrol 1 .............................................................................................................................. ........................34 t able 28. p ort 1 c ontrol 2 .............................................................................................................................. ........................34 t able 29. p ort 1 c ontrol 2 .............................................................................................................................. ........................34 t able 30. p ort 1 c ontrol 4 & vlan e ntry [b] ....................................................................................................................35 t able 31. i nternal u se r egister ............................................................................................................................... ..............36 t able 32. p ort 2 c ontrol 0 .............................................................................................................................. ........................36 t able 33. p ort 2 c ontrol 1 .............................................................................................................................. ........................37 t able 34. r eserved ............................................................................................................................... .....................................37 t able 35. p ort 2 c ontrol 2 & vlan e ntry [c] ....................................................................................................................38 t able 36. s witch mac a ddress ............................................................................................................................... ...............39 t able 37. p ort 3 c ontrol 0 .............................................................................................................................. ........................39 t able 38. p ort 3 c ontrol 1 .............................................................................................................................. ........................40 t able 39. r eserved ............................................................................................................................... .....................................40 t able 40. p ort 3 c ontrol 2 & vlan e ntry [d] ....................................................................................................................40 t able 41. i nternal u se r egister ............................................................................................................................... ..............41 t able 42. p ort 4 c ontrol 0 .............................................................................................................................. ........................42 t able 43. p ort 4 c ontrol 1 .............................................................................................................................. ........................42 t able 44. r eserved ............................................................................................................................... .....................................43 t able 45. p ort 4 c ontrol 2 & vlan e ntry [e].....................................................................................................................43 t able 46. i nternal u se r egister ............................................................................................................................... ..............44 t able 47. 802.1 p b ase p riority ............................................................................................................................... ..................44 t able 48. vlan e ntry [f] ............................................................................................................................ ............................44 t able 49. vlan e ntry [g] ............................................................................................................................ ...........................45 t able 50. vlan e ntry [h] ............................................................................................................................ ...........................45 t able 51. vlan e ntry [i] ............................................................................................................................ .............................46 t able 52. vlan e ntry [j]............................................................................................................................ .............................46 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller x track id: jatr-1076-21 rev. 1.2 t able 53. vlan e ntry [k] ............................................................................................................................ ...........................47 t able 54. vlan e ntry [l]............................................................................................................................ ............................47 t able 55. vlan e ntry [m]............................................................................................................................ ...........................48 t able 56. vlan e ntry [n] ............................................................................................................................ ...........................48 t able 57. vlan e ntry [o] ............................................................................................................................ ...........................49 t able 58. vlan e ntry [p] ............................................................................................................................ ............................49 t able 59. r egister d escriptions ............................................................................................................................... ..............50 t able 60. phy 0 r egister 0: c ontrol ............................................................................................................................... ......53 t able 61. phy 0 r egister 1: s tatus ............................................................................................................................... .........54 t able 62. phy 0 r egister 2: phy i dentifier 1.......................................................................................................................54 t able 63. phy 0 r egister 3: phy i dentifier 2.......................................................................................................................55 t able 64. phy 0 r egister 4: a uto -n egotiation a dvertisement ........................................................................................55 t able 65. phy 0 r egister 5: a uto -n egotiation l ink p artner a bility ..............................................................................56 t able 66. phy 0 r egister 16: g lobal c ontrol 0..................................................................................................................56 t able 67. phy 0 r egister 17: g lobal c ontrol 1..................................................................................................................58 t able 68. phy 0 r egister 18: g lobal c ontrol 2..................................................................................................................58 t able 69. phy 0 r egister 19: g lobal c ontrol 3..................................................................................................................59 t able 70. phy 0 r egister 22: p ort 0 c ontrol r egister 0 ...................................................................................................60 t able 71. phy 0 r egister 24: p ort 0 c ontrol r egister 1 & vlan id [a] m embership .................................................61 t able 72. phy 0 r egister 25: p ort 0 r egister c ontrol 2 & vlan id [a]........................................................................61 t able 73. phy 0 r egister 26: r eserved r egister .................................................................................................................62 t able 74. phy 0 r egister 26: vlan id [f] m embership ......................................................................................................62 t able 75. phy 0 r egister 27: r eserved r egister .................................................................................................................62 t able 76. phy 0 r egister 27: vlan id [f] ................................................................................................................ ............62 t able 77. phy 0 r egister 28: r eserved r egister .................................................................................................................63 t able 78. phy 0 r egister 28: vlan id [k] m embership .....................................................................................................63 t able 79. phy 0 r egister 29: r eserved r egister .................................................................................................................63 t able 80. phy 0 r egister 29: vlan id [k]................................................................................................................ ............63 t able 81. phy 0 r egister 30: r eserved r egister .................................................................................................................64 t able 82. phy 0 r egister 30: vlan id [p] m embership ......................................................................................................64 t able 83. phy 0 r egister 31: r eserved r egister .................................................................................................................64 t able 84. phy 0 r egister 31: vlan id [p] ................................................................................................................ ............64 t able 85. phy 1 r egister 16~17: i nternal u se r egister ....................................................................................................65 t able 86. phy 1 r egister 18~19: i nternal u se r egister ....................................................................................................65 t able 87. phy 1 r egister 23: g lobal o ption r egister 0.....................................................................................................66 t able 88. phy 1 r egister 24: p ort 1 c ontrol r egister 1 & vlan id [b] m embership ..................................................66 t able 89. phy 1 r egister 25: p ort 1 c ontrol r egister 2 & vlan e ntry [b]..................................................................67 t able 90. phy 1 r egister 26: r eserved r egister .................................................................................................................67 t able 91. phy 1 r egister 26: vlan id [g] m embership .....................................................................................................67 t able 92. phy 1 r egister 27: r eserved r egister .................................................................................................................68 t able 93. phy 1 r egister 27: vlan id [g]................................................................................................................ ............68 t able 94. phy 1 r egister 28: r eserved r egister .................................................................................................................68 t able 95. phy 1 r egister 28: vlan id [l] m embership ......................................................................................................68 t able 96. phy 1 r egister 29: r eserved r egister .................................................................................................................69 t able 97. phy 1 r egister 29: vlan id [l] ................................................................................................................ ............69 t able 98. phy 2 r egister 16~17: i nternal u se r egister ....................................................................................................70 t able 99. phy 2 r egister 18~19: i nternal u se r egister ....................................................................................................70 t able 100. phy 2 r egister 23: g lobal o ption r egister 1...................................................................................................71 t able 101. phy 2 r egister 24: p ort 2 c ontrol r egister 2 & vlan id [c] m embership ................................................71 t able 102. phy 2 r egister 25: p ort 2 c ontrol r egister 3 & vlan id [c] ......................................................................72 t able 103. phy 2 r egister 26: r eserved r egister ...............................................................................................................72 t able 104. phy 2 r egister 26: vlan id [h] m embership ...................................................................................................72 t able 105. phy 2 r egister 27: r eserved r egister ...............................................................................................................73 t able 106. phy 2 r egister 27: vlan id [h]................................................................................................................ ..........73 t able 107. phy 2 r egister 28: r eserved r egister ...............................................................................................................73 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller xi track id: jatr-1076-21 rev. 1.2 t able 108. phy 2 r egister 28: vlan id [m] m embership ...................................................................................................73 t able 109. phy 2 r egister 29: r eserved r egister ...............................................................................................................74 t able 110. phy 2 r egister 29: vlan id [m] ................................................................................................................ .........74 t able 111. phy 3 r egister 16~18: s witch mac a ddress ....................................................................................................75 t able 112. phy 3 r egister 19~21: i nternal u se r egister ..................................................................................................76 t able 113. phy 3 r egister 24: p ort 3 c ontrol r egister 1 & vlan id [d] m embership ................................................76 t able 114. phy 3 r egister 25: p ort 3 c ontrol r egister 2 & vlan id [d]......................................................................77 t able 115. phy 3 r egister 26: r eserved r egister ...............................................................................................................77 t able 116. phy 3 r egister 26: vlan id [i] m embership .....................................................................................................77 t able 117. phy 3 r egister 27: r eserved r egister ...............................................................................................................78 t able 118. phy 3 r egister 27: vlan id [i] ................................................................................................................ ...........78 t able 119. phy 3 r egister 28: r eserved r egister ...............................................................................................................78 t able 120. phy 3 r egister 28: vlan id [n] m embership ...................................................................................................78 t able 121. phy 3 r egister 29: r eserved r egister ...............................................................................................................79 t able 122. phy 3 r egister 29: vlan id [n]................................................................................................................ ..........79 t able 123. phy 4 r egister 16: i ndirect a ccess c ontrol ....................................................................................................80 t able 124. phy 4 r egister 17~20: i ndirect a ccess d ata ....................................................................................................81 t able 125. phy 2 r egister 20: 802.1 p b ase p riority ............................................................................................................81 t able 126. phy 4 r egister 24: p ort 4 c ontrol r egister 1 & vlan id [e] m embership ................................................82 t able 127. phy 4 r egister 25: p ort 4 c ontrol r egister 2 & vlan id [e] ......................................................................83 t able 128. phy 4 r egister 26: r eserved r egister ...............................................................................................................83 t able 129. phy 4 r egister 26: vlan id [j] m embership .....................................................................................................83 t able 130. phy 4 r egister 27: r eserved r egister ...............................................................................................................84 t able 131. phy 4 r egister 27: vlan id [j]................................................................................................................ ...........84 t able 132. phy 4 r egister 28: r eserved r egister ...............................................................................................................84 t able 133. phy 4 r egister 28: vlan id [o] m embership ...................................................................................................84 t able 134. phy 4 r egister 29: r eserved r egister ...............................................................................................................85 t able 135. phy 4 r egister 29: vlan id [o]................................................................................................................ ..........85 t able 136. phy 5 r egister 0: c ontrol ............................................................................................................................... ....86 t able 137. phy 5 r egister 1: s tatus ............................................................................................................................... .......87 t able 138. phy 5 r egister 2: phy i dentifier 1 .....................................................................................................................87 t able 139. phy 5 r egister 3: phy i dentifier 2 .....................................................................................................................87 t able 140. phy 5 r egister 4: a uto -n egotiation a dvertisement ......................................................................................88 t able 141. mii p ort nw ay m ode ............................................................................................................................... ..............89 t able 142. mii p ort f orce m ode ............................................................................................................................... ..............89 t able 143. mii r egister d efinition for phy 4 and phy 5.................................................................................................103 t able 144. pecl dc c haracteristics ............................................................................................................................... ...112 t able 145. smi r ead /w rite c ycles ............................................................................................................................... .......119 t able 146. 802.1q vlan t ag f rame f ormat .......................................................................................................................124 t able 147. ip v 4 f rame f ormat ............................................................................................................................... ...............124 t able 148. r eserved m ulticast a ddress .............................................................................................................................12 5 t able 149. l oop f rame f ormat ............................................................................................................................... ...............127 t able 150. s pd and b i -c olor l ink /a ct t ruth t able ..........................................................................................................130 t able 151. a n e xample u sing p ower t ransistor 2sb1188................................................................................................132 t able 152. e lectrical c haracteristics /r atings ...............................................................................................................133 t able 153. led t iming ............................................................................................................................... .............................136 t able 154. mii & smi dc t iming ............................................................................................................................... ............137 t able 155. p ackage d escription ............................................................................................................................... ............139 t able 156. pcb d escription ............................................................................................................................... ....................139 t able 157. a ssembly m at e r i a l ............................................................................................................................... ...............139 t able 158. s imulation a nalysis c onditions .......................................................................................................................140 t able 159. r esults ............................................................................................................................... ....................................140 t able 160. t ransformer v endors ............................................................................................................................... .........141 t able 161. o rdering i nformation ............................................................................................................................... ..........148 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller xii track id: jatr-1076-21 rev. 1.2 list of figures f igure 1. b lock d iagram ............................................................................................................................... ..........................6 f igure 2. p in a ssignments ............................................................................................................................... .........................7 f igure 3. p ort 4 o perating m ode o verview ........................................................................................................................93 f igure 4. t raditional a pplication ............................................................................................................................... .........99 f igure 5. d ual mii a pplication d iagram ..........................................................................................................................100 f igure 6. d ual mii m ode with 1 mii-mac + 1 mii-phy (100b ase -t utp) i nterfaces a pplication c ircuit ............101 f igure 7. d ual mii m ode with 1 mii-mac + 1 mii-phy (100b ase -fx m ode ) i nterfaces a pplication c ircuit .......101 f igure 8. d ual mii m ode with 1 mii-phy + 1 mii-phy (100b ase -t utp) i nterfaces a pplication c ircuit .............102 f igure 9. d ual mii m ode with 1 sni-phy + 1 mii-phy (100b ase -t utp) i nterfaces a pplication c ircuit .............102 f igure 10. r eset ............................................................................................................................... ........................................115 f igure 11. s tart and s top d efinition ............................................................................................................................... ....117 f igure 12. o utput a cknowledge ............................................................................................................................... ...........117 f igure 13. r andom r ead ............................................................................................................................... .........................118 f igure 14. s equential r ead ............................................................................................................................... ....................118 f igure 15. vlan g rouping e xample ............................................................................................................................... .....120 f igure 16. t agged and u ntagged p acket f orwarding when 802.1q t ag a wa r e vlan is d isabled ...........................122 f igure 17. i nput d rop vs . o utput d rop ............................................................................................................................... .126 f igure 18. l oop e xample ............................................................................................................................... .........................127 f igure 19. p ort 4 l oopback ............................................................................................................................... ....................128 f igure 20. r eg . 0.14 l oopback ............................................................................................................................... ................129 f igure 21. f loating and p ull -d own of led p ins ...............................................................................................................130 f igure 22. t wo p in b i - color led for spd f loating or p ull - high ..................................................................................131 f igure 23. t wo p in b i - color led for spd p ull - down ......................................................................................................131 f igure 24. u sing a pnp t ransistor to t ransform 3.3v i nto 1.8v....................................................................................132 f igure 25. r eception d ata t iming of mii/sni/smi i nterface ...........................................................................................136 f igure 26. t ransmission d ata t iming of mii/sni/smi i nterface .....................................................................................136 f igure 27. utp a pplication for t ransformer with c onnected c entral t ap ................................................................141 f igure 28. utp a pplication for t ransformer with s eparate c entral t ap ....................................................................142 f igure 29. 100b ase -fx with 3.3v f iber t ransceiver a pplication ...................................................................................143 f igure 30. 100b ase -fx with 5v f iber t ransceiver a pplication ......................................................................................144 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 1 track id: jatr-1076-21 rev. 1.2 1. general description the RTL8305SC is a 5-port fast ethernet switch contro ller that integrates memo ry, five macs, and five physical layer transceivers for 10b ase-t and 100base-tx operation into a single chip. all ports support 100base-fx, which shares pins (tx+-/rx+-) with utp ports and needs no sd+/- pins, a development using realtek proprietary technology. to compensate for the lack of auto-n egotiation in 100base-fx applications, the RTL8305SC can be fo rced into 100base-fx ha lf or full duplex mode, and can enable or disable flow control in fiber mode. the five ports are separated into three groups (groupx/g roupy/port4) for flexible port configuration using strapping pins upon reset. th e setgroup pin is used to select port members in groupx and groupy. when the port members have been determined, you may use a mode selection pin (gxmode/gymode/p4mode[1:0]) to select operati ng interfaces such as 10/100base-tx, 100base-fx. each group has four pins for selecting initial port status upon reset (aneg/force, 100/10, full/half, enable/disable flow control). upon reset, in additi on to using strapping pins, a cpu can also configure the RTL8305SC via the mdc/mdio interface. the fifth port (port 4) supports an external mac and an external phy interface. the external mac interface can be set to p hy mode mii, phy mode sni, or mac mode mii to work with a routing engine, homepna, or vdsl transceiver. the external phy interface can be set to phy mode mii in the digital interface, and utp or fiber in the differential interface. in order to accomplish diagnostics in complex network systems, the RTL8305SC also provide s a loopback feature in ea ch port for a variable cpu system. the RTL8305SC contains a 1k-entry address lookup table and supports a 16-en try cam to avoid hash collisions and to maintain forwarding performance. the 1k-entry table provide s read/write access from the smi interface, and each of the entr ies can be configured as a static entry. a static entry indicates that this entry is controlled by the external management processor and automatic aging and learning of the entry will not take place. the RTL8305SC suppor ts ieee 802.3x full-duplex flow control and back- pressure half-duplex flow contro l. a broadcast storm filtering func tion is provided to filter unusual broadcast storm issues, and an intelligent switch engine prevents head-of -line blocking problems. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 2 track id: jatr-1076-21 rev. 1.2 the RTL8305SC supports 16 vlan groups. these can be configured as port-based vlans and/or ieee 802.1q tag-based vlans. two ingress filtering an d egress filtering options provide flexible vlan configuration: ? ingress filtering option 1: the acceptable frame type of the ingress process can be set to ?admit all? or ?admit all tagged?. ? ingress filtering option 2: ?admit? or ?discard? frames associated with a vlan for which that port is not in the member set. ? egress filtering option 1: ?forward? or ?discard? arp broadcast frames. ? egress filtering option 2: ?forward? or ?discard? leaky vlan frames. the RTL8305SC supports several type s of qos functions with two-le vel priority queues to improve multimedia or real-time networking applications. the qos functions are based on: ? port-based priority ? 802.1q vlan priority tag ? the tos/ds (diffserv) field of tcp/ip when the qos function is enabled, a vlan tag can be inserted or removed at the output port. the RTL8305SC will insert a po rt vid (pvid) for untagged frames or remove the tag from tagged frames. the RTL8305SC also supports a special insert vlan tag function to separate traffic from wan and lan sides in router and gateway applications. in router applications, the router may want to know which input port this packet came from. the RTL8305SC supports port vid (pvid) for each port a nd can insert a pvid in the vlan tag on egress. using this function, vid information carried in the vlan tag will be changed to pvid. the RTL8305SC also provides an option to admit vlan ta gged packets with a specific pvid only. if this function is enabled, it will drop non-tagged p ackets and packets with an incorrect pvid. maximum packet length can be 153 6 or 1552 bytes according to the in itial configurati on (strapping upon reset). the filtering function is supported for th e 802.1d specified reserved multicast addresses (01-80- c2-00-00-02 and 01-80-c2-00-00- 04 to 01-80-c2-00-00-0f). www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 3 track id: jatr-1076-21 rev. 1.2 the RTL8305SC provides flexible led functions for diagnostics. these include: three combinations of link, activity, speed, duplex and collis ion, that are ideal for bi-color led displays. the RTL8305SC also provides a loop detection f unction and alarm, for network existence notification, with an output pin that can be designed as a visual led or a status input pin for a cpu. a power saving mode is implemented on a per-port basi s. each port automatically enters power saving mode 10 seconds after the cable is disconnected from it. the RTL8305SC also implements a power down mode on a per-port basis. users can set mii reg.0.11 to force the corr esponding port to enter power down mode, which disables all transmit/receive functi ons, except smi (mdc/mdio management interface). each physical layer channel of the RTL8305SC consis ts of a 4b5b encoder/ decoder, a manchester encoder/decoder, a scrambler/de-scrambler, a transmit output driver, output wave shaping filters, a digital adaptive equalizer, a pll circuit, and a dc restorati on circuit for clock/data r ecovery. friendly crossover auto detection and correction functions ar e also supported for easy cable connection. the integrated chip benefits from low power consump tion, advanced functions with flexible configuration for 5-port soho switch, home gateway, xdsl/c able router, and othe r ia applications. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 4 track id: jatr-1076-21 rev. 1.2 2. features 5-port integrated switch controller with memory and transceiver for 10base-t and 100base-tx with: 5-port 10/100m utp or 4-port 10/100m utp + 1-port mii/sni or 4-port 10/100m utp + 1-port mac mii/sni + 1-port phy mii supports the fifth port mac circuit as phy mode mii, sni for router applications, and mac mode mii for homepna or vdsl solutions supports the fifth port phy circuit as phy mode mii for router and gateway applications all ports support 100base-fx with optional flow control enable/disable and full/half-duplex setting supports fefi function for fiber application non-blocking wire-speed reception and transmission and non-head-of-line- blocking forwarding fully compliant with ieee 802.3/802.3u auto-negotiation function built-in high-efficiency sram for packet buffer, with 1k-entry lookup table and 16-entry cam supports broadcast storm filtering function flow control fully supported: half duplex: back pressure flow control full duplex: ieee 802.3x flow control supports smi (serial management interface: mdc/mdio) for programming and diagnostics supports loop detection function with one led to indicate the existence of a loop supports mac and phy loopback function for diagnosis supports up to 16 vlan groups flexible 802.1q port/tag-based vlan arp vlan for broadcast packets leaky vlan for unicast packets vlan tag insert/remove function supports qos function on each port: qos based on: (1) port-based, (2) vlan tag, (3) tcp/ip header?s tos/ds supports two-level priority queues weighted round robin service www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 5 track id: jatr-1076-21 rev. 1.2 supports special vlan tag insert or remove function on per-port basis (egress) to separa te wan traffic from lan traffic optional 1536 or 1552 byte maximum packet length supports reserved control frames (did=0180c2000003~0180c200000f) filtering function flexible led indicators for link, activity, speed, full/half duplex, and collision leds blink upon reset for led diagnostics supports two power reduction methods: power saving mode by cable detection power down mode (via phy register 0.11) robust baseline wander correction for improved 100base-tx performance optional mdi/mdix auto crossover for plug-and-play physical layer port polarity detection and correction function optional eeprom interface for configuration 25mhz crystal or 3.3v osc input single 3.3v power input can be transformed to 1.8v via a low-cost external bjt transistor low power, 1.8/3.3v, 0.18m cmos technology, 128-pin pqfp package www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 6 track id: jatr-1076-21 rev. 1.2 3. block diagram 10base-t or 100base-t phyceiver mac0 mac4 mac3 mac2 mac1 waveform shaping mode select circuit lookup table led control global function packet buffer led_blnk_time en_rst_blnk sel_miimac x2 x1 ck25mout reset# ibref enbkprs disbrdctrl p4mode[1:0] led_spd[4:0] switch engine2 switch engine0 switch engine1 switch engine3 switch engine4 rx+-[0] tx+-[0] rx+-[1] tx+-[1] rx+-[2] tx+-[2] rx+-[3] tx+-[3] rx+-[4] tx+-[4] led_act[4:0] led_dup[4:0] led_add[4:0] disdualmii r phy mode mii/sni mac mode mii mcol/pcol mtxc/prxc mtxd[3:0]/prxd[3:0] mtxen/prxdv mrxc/ptxc mrxdv/ptxen mrxd[3:0]/ptxd[3:0] p4lnksta# p4dupsta/p4full p4spdsta/p4spd100 p4flctrl/p4enfc phy mode mii phy2pcol phy2prxc phy2prxd[3:0] phy2prxdv phy2ptxc phy2ptxen phy2ptxd[3:0] 10base-t or 100base-t phyceiver 10base-t or 100base-t phyceiver 10base-t or 100base-t phyceiver 10base-t or 100base-t phyceiver phy interface mac interface figure 1. block diagram www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 7 track id: jatr-1076-21 rev. 1.2 4. pin assignments enforward/led_add[0] dgnd gyfull/led_dup[1] gxfull/led_spd[1] gyspd100/led_act[1] gxspd100/led_add[1] gyaneg/led_dup[2] dvdd33 gxaneg/led_spd[2] p4aneg/led_act[2] bcindrop/led_act[0] ibref agnd vctrl agnd x2 x1 avdd18 hvdd33 led_dup[0] max1536/led_spd[0] avdd18 rx ip[0] rxin[0] avdd18 mtxd[1]/prxd[1]/ledmode[1] mrxd[0]/ptxd[0] mtxd[0]/prxd[0]/ledmode[0] 103 124 123 122 121 125 128 127 126 113 112 111 110 109 108 107 106 105 104 114 120 119 118 117 116 115 90 89 79 83 80 82 84 81 86 85 87 88 102 101 91 95 92 94 96 93 98 97 99 100 78 77 67 71 68 70 72 69 74 73 75 76 66 65 1 11 9 8 7 6 5 4 3 2 10 12 22 21 20 19 18 17 16 15 14 13 23 33 32 31 30 29 28 27 26 25 24 34 38 37 36 35 mtxd[3]/prxd[3]/p4irtag[1] 55 59 56 58 60 57 62 61 63 64 54 53 47 48 50 49 51 52 43 44 46 45 39 40 42 41 mrxc/ptxc mtxd[2]/prxd[2]/p4irtag[0] mcol/pcol mrxdv/ptxen dvdd33 mrxd[1]/ptxd[1] dgnd dvdd18 p4spdsta/p4spd100 p4dupsta/p4full dgnd p4lnksta# mtxc/prxc mtxen/prxdv dvdd18 p4mode[1] p4flctrl/p4enfc p4mode[0] dgnd reset# disdualmii itest4 RTL8305SC itest3 agnd rxin[1] rx ip[1] agnd txop[1] txon[1] avdd18 avdd18 txon[0] txop[0] avdd18 txon[3] avdd18 avdd18 txon[2] txop[2] agnd rx ip[2] rxin[2] avdd18 txop[3] agnd rx ip[4] rxin[4] avdd18 avdd18 rxin[3] rx ip[3] agnd avdd18 txon[4] osci ck25mout txop[4] itest1 itest2 dtest2 dtest1 led_add[2]/disleaky loopled#/endefer d i sport pr i [ 3] (phy2ptxd[2]) en_autoxover phy2prxdv /disbrdctrl phy2prxd[1] /gxenfc phy2prxd[2] /gyenfc phy2pcol /led_blnk_time d i sport pr i [ 0] (phy2ptxen) phy2ptxc /qweight[1] d i sport pr i [ 1] (phy2ptxd[0]) d i sport pr i [ 2] (phy2ptxd[1]) dvdd33 d i sport pr i [ 4] (phy2ptxd[3]) mrxd[3]/ptxd[3] en_rst_blnk sel_m i i m a c#/d i sdspri dvdd18 scl _m dc phy2prxd[0] /eneeprom mrxd[2]/ptxd[2] itest5 dgnd led_add[4]/distagpri led_dup[4]/setgroup led_act[4] dgnd led_add[3]/gxmode led_spd[4]/disvlan led_spd[3]/disarp led_act[3]/en48pass1 led_dup[3]/gymode dvdd18 phy2prxc /qweight[0] dgnd phy2prxd[3] /enbkprs sd a _m d i o itest6 figure 2. pin assignments note: when disdualmii=1, the function of pins 83~86 and pin 88 follows the names before the parenthesis ?( )?. when disdualmii=0, pin names in parenthesis ?( )? will become functional and original pin functions will not apply. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 8 track id: jatr-1076-21 rev. 1.2 ?type? codes used in the following tables: a=analog; d=digital, i=input; o=output, pu=internal pull-up, pd=internal pull-down. table 1. pin assignments name pin no. type name pin no. type avdd18 rxin[0] rxip[0] agnd txop[0] txon[0] avdd18 avdd18 txon[1] txop[1] agnd rxip[1] rxin[1] avdd18 avdd18 rxin[2] rxip[2] agnd txop[2] txon[2] avdd18 avdd18 txon[3] txop[3] agnd rxip[3] rxin[3] avdd18 avdd18 rxin[4] rxip[4] agnd txop[4] txon[4] avdd18 itest1 itest2 itest3 dgnd reset# itest4 disdualmii dvdd18 p4mode[1] p4mode[0] p4flctrl/p4enfc p4spdsta/p4spd100 p4dupsta/p4full p4lnksta# dgnd mtxc/prxc mtxen/prxdv/internal dvdd18 mtxd[0]/prxd[0]/ledmode[0] mtxd[1]/prxd[1]/ledmode[1] mtxd[2]/prxd[2]/p4irtag[0] mtxd[3]/prxd[3]/p4irtag[1] mcol/pcol mrxc/ptxc mrxdv/ptxen mrxd[0]/ptxd[0] dvdd33 mrxd[1]/ptxd[1] dgnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 avdd ai ai agnd ao ao avdd avdd ao ao agnd ai ai avdd avdd ai ai agnd ao ao avdd avdd ao ao agnd ai ai avdd avdd ai ai agnd ao ao avdd dgnd i i pu dvdd i pu i pu i pu i pu i pu i pu dgnd i/o pu i/o pu dvdd i/o pu i/o pu i/o pu i/o pu i/o pd i/o pu i pd i pu dvdd i pu dgnd itest5 mrxd[2]/ptxd[2] mrxd[3]/ptxd[3] sel_miimac#/disdspri en_autoxover dvdd18 en_rst_blnk itest6 phy2prxd[0]/eneeprom scl_mdc sda_mdio phy2prxd[1]/gxenfc phy2prxd[2]/gyenfc phy2prxd[3]/enbkprs dgnd phy2prxdv/disbrdctrl phy2prxc/qweight[0] phy2ptxc/qweight[1] disportpri[0] ( phy2ptxen ) disportpri[1] ( phy2ptxd[0] ) disportpri[2] ( phy2ptxd[1] ) disportpri[3] ( phy2ptxd[2] ) dvdd33 disportpri[4] ( phy2ptxd[3] ) phy2pcol/led_blnk_time loopled#/endefer led_add[4]/distagpri led_act[4] led_spd[4]/disvlan dgnd led_dup[4]/setgroup led_add[3]/gxmode led_act[3]/en48pass1 led_spd[3]/disarp led_dup[3]/gymode dvdd18 led_add[2]/disleaky dgnd led_act[2]/p4aneg led_spd[2]/gxaneg led_dup[2]/gyaneg dvdd33 led_add[1]/gxspd100 led_act[1]/gyspd100 led_spd[1]/gxfull led_dup[1]/gyfull led_add[0]/enforward dgnd led_act[0]/bcindrop led_spd[0]/max1536 led_dup[0] ck25mout osci hvdd33 avdd18 x1 x2 agnd vctrl dtest2 dtest1 agnd ibref avdd18 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 i pu i pu i/o pu i pu dvdd i pu i pu i/o pu i/o pu i pu i pu i pu dgnd i pu i pu i pu i pu i pu i pu i pu dvdd i pu i pu i/o pu i/o pu i/o pu i/o pu dgnd i/o pu i/o pu i/o pu i/o pu i/o pu dvdd i/o pu dgnd i/o pu i/o pu i/o pu dvdd i/o pu i/o pu i/o pu i/o pu i/o pu dgnd i/o pu i/o pu i/o pu o i avdd avdd i o agnd o agnd a avdd www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 9 track id: jatr-1076-21 rev. 1.2 5. pin descriptions ?type? codes used in the following tables: a=analog; d=digital, i=input; o=output, pu=internal pull-up, pd=internal pull-down. upon reset: defined as a short time after th e end of a hardware reset. after reset: defined as the time after th e specified ?upon reset? time. 5.1. media connection pins table 2. media connection pins pin name pin no. type drive (ma) description rxip[4:0] rxin[4:0] 2, 3, 12, 13, 16, 17, 26, 27, 30, 31 i differential receive data input shared by 100base-tx, 10base-t, and 100base-fx. utp or fx depends on pin gxmode/gymode/p4mode[1:0]. txop[4:0] txon[4:0] 5, 6, 9, 10, 19, 20, 23, 24, 33, 34 o differential transmit data output shared by 100base-tx, 10base-t, and 100base-fx. utp or fx depends on pin gxmode/gymode/p4mode[1:0]. 5.2. port 4 configuration pins table 3. port 4 configuration pin definitions pin name pin no. type drive (ma) description port 4 configuration pin definitions disdualmii 42 i pu disable dual mii interface function this pin disables or enables th e dual mii interface function of port 4. 1: disable 0: enable when enabled, the mac circuit of port 4 can be set as mac mode mii, phy mode mii, or phy mode sni. the phy circuit of port 4 is set as phy mode mii. the phy circuit of port 4 can optionally be set as utp or fiber mode according to the p4mo d[1:0] configuration. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 10 track id: jatr-1076-21 rev. 1.2 pin name pin no. type drive (ma) description port 4 configuration pin definitions p4mode[1:0] 44, 45 i pu when disdualmii=1: select port 4 mac circuit operating mode: 11: utp/mac mode mii 10: 100base-fx mode 01: phy mode mii 00: phy mode sni when disdualmii=0, i. select port 4 mac circuit operating mode: 1x: mac mode mii 01: phy mode mii 00: phy mode sni 11: port 4 phy circuit operating mode: note: provides phy mode mii only when disdualmii=0. p4lnksta# 49 i pu port 4 link status for mac this pin determines the link status of the port 4 mac in real- time when the port 4 mac is in mac mode mii/phy mode mii/phy mode sni regardless of whether the port 4 phy circuit interface is disabled or enabled in phy mode mii. this pin is low active. pulling this pin down sets the link status of the phy 5 mii register to 1.2. 1: no link 0: link p4mode[1:0]=11 and disdualmii=1 (utp/mac mode mii) this pin determines the link status of mac mode mii only in real time. the link status of utp mode is provided by the internal phy in real time. if both the utp and mii ports are linked ok, utp has higher priority. p4mode[1:0]=11 and disdualmii=0 (mac mode mii) this pin determines the link status of mac mode mii only in real time. p4mode[1:0]=10 (100base-fx mode) this pin does nothing. the internal phy will provide the link status to the mac in real time. p4mode[1:0]=01 (phy mode mii) this pin determines the link status of port 4 in real time. p4mode[1:0]=00 (phy mode sni) this pin determines the link status of port 4 in real time. when disdualmii=1, this pin should be left floating in utp or fx mode, and pulled down in mac mode mii/phy mode mii/phy mode sni. regardless of whether disdualmii=1 or=0, this pin provides the link status to the port 4 mac part in phy 5 mii register 1.2 when the port 4 mac part is configured in mac mode mii/phy mode mii/phy mode sni. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 11 track id: jatr-1076-21 rev. 1.2 pin name pin no. type drive (ma) description port 4 configuration pin definitions p4dupsta 48 i pu port 4 duplex status port 4 initial configuration pin for duplex upon reset for phy in utp or fx mode, and strap duplex status for mac of other modes upon reset. 1: full duplex 0: half duplex p4mode[1:0]=11 (utp/mac mode mii) this pin provides the initial duplex configuration of the phy part upon reset when port 4 operates in utp mode. if port 4 operates in mac mode mii, this pin straps the initial duplex status for the mac part upon reset. p4mode[1:0]=10 (100base-fx mode) this pin provides the initial duplex register configuration of the phy part upon reset (fx). the duplex status of the mac part is provided by the internal phy in real time after reset. p4mode[1:0]=01 (phy mode mii) this pin straps the initial duplex status of port 4 upon reset. p4mode[1:0]=00 (phy mode sni) this pin straps the initial duplex status of port 4 upon reset. in mac mode mii/phy mode mii/phy mode sni, the configuration of this pin will set the duplex status of the internal register upon reset. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 12 track id: jatr-1076-21 rev. 1.2 pin name pin no. type drive (ma) description port 4 configuration pin definitions p4spdsta 47 i pu port 4 speed status port 4 initial configuration pin for speed status upon reset for phy of utp mode only, and strap speed status for mac of other modes upon reset. 1: 100mbps 0: 10mbps p4mode[1:0]=11 (utp/mac mode mii) this pin provides the initial speed configuration of the phy part upon reset when port 4 operates in utp mode. if port 4 operates in mac mode mii, this pin straps the initial speed status for the mac part upon reset. p4mode[1:0]=10 (100base-fx mode) the speed is dedicated to 100m and this pin should be left floating as it is irrelevant. p4mode[1:0]=01 (phy mode mii) this pin straps the initial speed status of port 4 upon reset. p4mode[1:0]=00 (phy mode sni) the speed is dedicated to 10mhz. this pin should be pulled down. in order to provide 100m as the default value for phy, this pin is set as high active. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 13 track id: jatr-1076-21 rev. 1.2 pin name pin no. type drive (ma) description port 4 configuration pin definitions p4flctrl/ p4enfc 46 i pu port 4 flow control port 4 initial configuration pin for flow control upon reset for phy of utp and fx mode, and strap flow control status for mac of other modes upon reset. 1: enable flow control ability 0: disable flow control ability p4mode[1:0]=11 (utp/mac mode mii) this pin provides the initial flow control configuration of the phy part upon reset when port 4 operates in utp mode. if port 4 operates in mac mode mii, this pin straps the initial flow control status for the mac part upon reset. p4mode[1:0]=10 (100base-fx mode) this pin provides the initial configuration of flow control for the phy part upon reset (fx). p4mode[1:0]=01 (phy mode mii) this pin straps the initial flow control status of port 4 upon reset. p4mode[1:0]=00 (phy mode sni) flow control should be disabled. this pin must be pulled down. in order to enable flow control ability for the phy, this pin is set as high active. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 14 track id: jatr-1076-21 rev. 1.2 pin name pin no. type drive (ma) description port 4 configuration pin definitions sel_miimac#/ disdspri /(p4phy_ mode) 68 i/o pu 4 output after reset = sel_miimac# used for led when p4mode[1:0]=11 and disdualmii=1, this pin indicates whether the utp path or the mii mac path is selected. otherwise, this pin has no use. the led statuses are represen ted as active-low or high depending on input strapping if input=1: output 0=mii mac port is selected. 1=utp is selected. if input=0: output 1=mii mac port is selected. 0=utp is selected. when p4mode[1:0]=11 and disdualmii=1, the RTL8305SC supports utp/mii mac auto-detection function via the link status of port 4 utp and the p4lnksta# pin setting. utp has higher priority than mac mode mii. input upon reset when disdualmii=1, disdspri. disable differentiated service priority. 1: disable ds priority 0: enable ds priority input upon reset when disdualmii=0, p4phy_mode. select the operating mode of port 4 differential pair. 1: utp mode 0: fx mode 5.3. port 4 mac circuit interface pins the external device must be 3.3v compatible si nce the digital output of the RTL8305SC is 3.3v. table 4. port 4 mac circuit interface pin definitions pin name pin no. type drive (ma) description mrxd[3:0]/ ptxd[3:0] 61, 63, 66, 67 i pu for mac mode mii, these pins are mrxd[3:0], mii receive data nibble. for phy mode mii, these pins are ptxd[3:0], mii transmit data nibble. for phy mode sni, ptxd[0] is serial transmit data. mrxdv/ptxen 60 i pd for mac mode mii, this pin represents mrxdv, mii receive data valid. for phy mode mii, this pin re presents ptxen, mii transmit enable. for phy mode sni, this pin represents ptxen, transmit enable. mrxc/ptxc 59 i/o pu 8 for mac mode mii, this is a receive clock (mrxc acts as input). for phy mode mii/phy mode sni, it is a transmit clock (ptxc acts as output). www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 15 track id: jatr-1076-21 rev. 1.2 pin name pin no. type drive (ma) description mcol/pcol 58 i/o pd 4 for mac mode mii, this pin repr esents mcol collision (acts as input). for phy mode mii/phy mode sni, this pin represents pcol collision (acts as output). mtxd[3]/prxd[3] /p4irtag[1] mtxd[2]/prxd[2] /p4irtag[0] 57 56 i/o pu 4 output after reset. for mac mode mii (p4mode[1:0]=11), these pins are mtxd[3:0], mii transmit data of mac. for phy mode mii (p4mode[1:0]=01), these pins are prxd[3:0], mii receive data of phy. for phy mode sni (p4mode[1:0]=00), prxd[0] is sni serial receive data. input upon reset: p4irtag[1:0] insert/remove vlan tags of port 4. 11=do not insert/remove vlan tags to/from packets. 10=insert vlan tags to non-tagged packets. 01=remove tag from tagged packet. 00=replace the vlan tags for tagged packets and insert a vlan tag to non-tagged packets. these pins are used for port 4 only. use serial eeprom for other ports. mtxd[1]/prxd[1] /ledmode[1] mtxd[0]/prxd[0] /ledmode[0] 55 54 i/o pu 4 output after reset. for mac mode mii (p4mode[1:0]=11), these pins are mtxd[3:0], mii transmit data of mac. for phy mode mii (p4mode[1:0]=01), these pins are prxd[3:0], mii receive data of phy. for phy mode sni (p4mode[1:0]=00), prxd[0] is sni serial receive data. input upon reset: ledmode[1:0] each port has four led indicator pins. each pin has different indicator meanings set by pins, ledmode[1:0]. ledmode[1:0]=11: speed + link/act + duplex/col + link/act/spd. ledmode[1:0]=10: speed + act + duplex/col+bi-color link/active. ledmode[1:0]=01: speed + rxact + txact + link. ledmode[1:0]=00: reserved. all led statuses are represented as active-low or high depending on input strapping, except bi-color link/act in bi-color led mode, whose polarity depends on spd status. link/act/spd: link, activity, and speed indicator. on for link established. blinking every 43ms when the corresponding port is transmitting or receiving at 100mbps. blinking every 120ms when the port is transmitti ng or receiving at 10mbps. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 16 track id: jatr-1076-21 rev. 1.2 pin name pin no. type drive (ma) description mtxen/prxdv /internal 52 i/o pd 4 output after reset. for mac mode mii, this pin re presents mtxen, mii transmit enable. for phy mode mii, this pin represents prxdv, mii received data valid. for phy mode sni, this pin represents prxdv, received data valid. input upon reset. internal use mtxc/prxc 51 i/o pu 8 for mac mode mii, it is a transmit clock (mtxc acts as input). for phy mode mii/phy mode sni, it is a receive clock (prxc acts as output). 5.4. port 4 phy circuit interface pins the external device must be 3.3v compatible as the digital output of the RTL8305SC is 3.3v. table 5. port 4 phy circ uit interface pin definitions pin name pin no. type drive (ma) description disportpri[4] (phy2ptxd[3]) 88 i pu - disdualmii=1, enable port based priority qos function of port 4. disportpri[4]: 1=disable port 4 priority. 0=enable port 4 priority. disdualmii=0, phy mode mii transmit data nibble. for phy mode mii, this pin is phy2ptxd[3]. disportpri[4] power on strapping is not supported when disdualmii=0. this configuration can be set from the mii register. disportpri[3] (phy2ptxd[2]) 86 i pu - disdualmii=1, enable port based priority qos function of port 3. disportpri[3]: 1=disable port 3 priority. 0=enable port 3 priority. disdualmii=0, phy mode mii transmit data nibble. for phy mode mii, this pin is phy2ptxd[2]. disportpri[3] power on strapping is not supported when disdualmii=0. this configuration can be set from the mii register. disportpri[2] (phy2ptxd[1]) 85 i pu - disdualmii=1, enable port based priority qos function of port 2. disportpri[2]: 1=disable port 2 priority. 0=enable port 2 priority. disdualmii=0, phy mode mii transmit data nibble. for phy mode mii, this pin is phy2ptxd[1]. disportpri[2] power on strapping is not supported when disdualmii=0. this configuration can be set from the mii register. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 17 track id: jatr-1076-21 rev. 1.2 pin name pin no. type drive (ma) description disportpri[1] (phy2ptxd[0]) 84 i pu - disdualmii=1, enable port based priority qos function of port 1. disportpri[1]: 1=disable port 1 priority. 0=enable port 1 priority. disdualmii=0, phy mode mii transmit data nibble. for phy mode mii, this pin is phy2ptxd[0]. disportpri[1] power on strapping is not supported when disdualmii=0. this configuration can be set from the mii register. disportpri[0] (phy2ptxen) 83 i pu - disdualmii=1, enable port based priority qos function of port 0. disportpri[0]: 1=disable port 0 priority. 0: enable port 0 priority. disdualmii=0, phy mode mii transmit data enable. for phy mode mii, this pin is phy2ptxen. disportpri[0] power on strapping is not supported when disdualmii=0. this configuration can be set from the mii register. for dual mii application, this pin should be pulled low (about 1k ohm) in the external circuit. phy2pcol /led_blnk_ time 89 i/o pu 4 output after reset: disdualmii=0, phy mode mii pcol. for phy mode mii, this pin represents pcol collision (acts as output). input upon reset: led blink time. this pin selects the blinking speed of the activity and collision leds. 1: on 43ms, then off 43ms 0: on 120ms, then off 120ms power on strapping is independent of disdualmii configuration. phy2ptxc /qweight[1] phy2prxc /qweight[0] 82 81 i/o pu 8 output after reset: disdualm ii=0, phy mode mii transmit/ receive data clock. for phy mode mii, this is transmit/receive data clock, ptxc/prxc (acts as output). input upon reset: weighted round robin ratio of priority queue. the frame service rate of high-priority queue: low-priority queue qweight[1:0]=11: 16:1 qweight[1:0]=10: always high priority queue first qweight[1:0]=01: 8:1 qweight[1:0]=00: 4:1 power on strapping is independent of disdualmii configuration. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 18 track id: jatr-1076-21 rev. 1.2 pin name pin no. type drive (ma) description phy2prxd[3] /enbkprs 78 i/o pu 4 output after reset: disdualmii=0, phy mode mii receive data nibble (acts as output). for phy mode mii, this pin is phy2prxd[3]. input upon reset: enable back pressure. this pin sets back pressure in half duplex mode on all utp ports. 1: enable 0: disable power on strapping is independent of disdualmii configuration. phy2prxd[2] /gyenfc 77 i/o pu 4 output after reset: disdualmii=0, phy mode mii receive data nibble (acts as output). for phy mode mii, this pin is phy2prxd[2]. input upon reset: groupy enable flow control ability. 1: enable reg4.10 (nway full duplex only), or ?enable force full pause ability of force mode (utp force mode or fx mode)?, or ?enable force half back pressure ability of force mode (utp force mode or fx mode)? 0: disable reg4.10 (nway full duplex only), or ?disable force full pause ability of force mode (utp force mode or fx mode)?, or ?disable force half back pressure ability of force mode (utp force mode or fx mode)? strap after reset for initial value of group y ?utp nway full?, or ?utp force full or half mode?, or ?fx full or half mode?. power on strapping is independent of disdualmii configuration. phy2prxd[1] /gxenfc 76 i/o pu 4 output after reset: disdualmii=0, phy mode mii receive data nibble (acts as output). for phy mode mii, this pin is phy2prxd[1]. input upon reset: groupx enable flow control ability: 1: enable reg4.10 (nway full duplex only), or ?enable force full pause ability of force mode (utp force mode or fx mode)?, or ?enable force half back pressure ability of force mode (utp force mode or fx mode)? 0: disable reg4.10 (nway full duplex only), or ?disable force full pause ability of force mode (utp force mode or fx mode)?, or ?disable force half back pressure ability of force mode (utp force mode or fx mode)? strap after reset for initial value of group x ?utp nway full?, or ?utp force full or half mode?, or ?fx full or half mode?. power on strapping is independent of disdualmii configuration. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 19 track id: jatr-1076-21 rev. 1.2 pin name pin no. type drive (ma) description phy2prxd[0] /eneeprom 73 i/o pu 4 disdualmii=0, phy m ode mii receive data nibble (acts as output). for phy mode mii, this pin is phy2prxd[0]. enable eeprom: this pin sets the RTL8305SC to enable loading of the serial eeprom upon reset. 1: enable 0: disable these pins have internal 75k ohm pull-high resistors. power on strapping is independent of disdualmii configuration. phy2prxdv /disbrdctrl 80 i/o pu 4 disdualmii=0, phy mode mii receive data valid. for phy mode mii, this pin represents prxdv. disable broadcast storm control. 1: disable 0: enable the RTL8305SC will disable this function when pin disbrdctrl is left floating. this pin has an internal 75k ohm pull-high resistor. power on strapping is independent of disdualmii configuration. 5.5. miscellaneous pins table 6. miscellaneous pins pin name pin no. type drive (ma) description x1 120 i a 25mhz crystal input the clock tolerance is +-50ppm. when using an oscillator, this pin should be tied to ground. x2 121 o for crystal input when using an oscillator, this pin should be left floating. osci 117 i a 25mhz clock from oscillator is fed to this pin the x1 should be tied to ground and x2 should be left floating in this application. if a 25mhz clock is from crystal via x1 and x2, this pin should be left floating. ck25mout 116 o 8 a 25mhz clock output this pin is used to support an extra 25m clock for an external device (for example: homepna phy). if this clock output is not used, this pin should be left floating. reset# 40 i active low reset signal to complete the reset function, this pin must be asserted for at least 1ms. after reset, about 30ms is needed for the RTL8305SC to complete internal test functions and initialization. this pin is a schmitt input. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 20 track id: jatr-1076-21 rev. 1.2 pin name pin no. type drive (ma) description ibref 127 a control transmit output waveform vpp this pin should be grounded through a 1.96k ? resistor. vctrl 123 o 4 voltage control to external regulator this signal controls a power pnp transistor to generate the 1.8v power supply. itest1 36 reserved pin for internal use. should be left floating itest2 37 reserved pin for internal use. should be left floating itest3 38 reserved pin for internal use. should be left floating itest4 41 reserved pin for internal use. should be left floating itest5 65 reserved pin for internal use. should be left floating itest6 72 reserved pin for internal use. should be left floating dtest2 124 reserved pin for internal use. should be left floating dtest1 125 reserved pin for internal use. should be left floating 5.6. port led pins each port has four led indicator pi ns. each pin may have different i ndicator meanings as set by pins ledmode[1:0]. all led statuses are represented as active-low or high depending on input stra pping, except bi-color link/act in bi-color led mode, whose polarity de pends on spd status. those pins that are dual function pins are output for led or input for strapping. below are led descriptions only. table 7. port led pins pin name pin no. type drive (ma) description led_spd[4:0]/? 93, 98, 104, 109, 114 i/o pu 4 output after reset = used for 1 st led. ledmode[1:0]=11 -> speed (on=100, off=10) ledmode[1:0]=10 -> speed (on=100, off=10) ledmode[1:0]=01 -> speed (on=100, off=10) ledmode[1:0]=00 -> reserved input upon reset = refer to table 9, on page 22, and table 10, on page 24. led_act[4:0]/? 92, 97, 103, 108, 113 i/o pu 4 output after reset = used for 2 nd led. ledmode[1:0]=11 -> link/act: (on=link, off=no link, flash=tx or rx activity) ledmode[1:0]=10 -> act: (off=no activity, on=tx or rx activity) ledmode[1:0]=01 -> rxact: (off=no activity, on=rx activity) ledmode[1:0]=00 -> reserved input upon reset = refer to table 9, on page 22, and table 10, on page 24. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 21 track id: jatr-1076-21 rev. 1.2 pin name pin no. type drive (ma) description led_dup[4:0]/? 95, 99, 105, 110, 115 i/o pu 4 output after reset = used for 3 rd led. ledmode[1:0]=11 -> duplex/col: (on=full, off=half with no collision, flash=collision) ledmode[1:0]=10 -> duplex/col: (on=full, off=half with no collision, flash=collision) ledmode[1:0]=01 -> txact: (off=no activity, on=tx activity) ledmode[1:0]=00 -> reserved input upon reset = refer to table 9, on page 22, and table 10, on page 24. led_add[4:0]/.. 91, 96, 101, 107, 111 i/o pu 4 output after reset = used for 4 th led. ledmode[1:0]=11 -> link/act/spd: on for link established. blinking every 43ms when the corresponding port is transmitting or receiving at 100mbp s. blinking every 120ms when the port is transmitting or receiving at 10mbps. ledmode[1:0]=10 -> bi-color link/active: polarity depends on spd status. ledmode[1:0]=01 -> link: (on=link, off=no link) ledmode[1:0]=00 -> reserved input upon reset = refer to table 9, on page 22, and table 10, on page 24. loopled# /endefer 90 i/o pu 4 output after reset = loopled# used for led. if the loop detection function is enabled, this pin indicates whether a network loop is detected or not. otherwise, this pin is of no use. the led statuses are represented as active-low or high depending on input strapping. => if input=1: output 0=network loop is detected. 1=no loop. => if input=0: output 1=network loop is detected. 0=no loop. input upon reset = enable defer 1: enable carrier sense deferring function for half duplex back pressure. 0: disable carrier sense deferring function for half duplex back pressure. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 22 track id: jatr-1076-21 rev. 1.2 5.7. serial eeprom and smi pins as the output of the RTL8305SC is 3.3v, the seri al eeprom and external device must be 3.3v compatible. table 8. serial eeprom and smi pins pin name pin no. type drive (ma) description scl_mdc 74 i/o pu 4 scl or mdc this pin is tri state when pin reset#=0. when pin eneeprom=1, this pin becomes scl (output) to load the serial eeprom upon reset. then this pin changes to mdc (input) after reset. when pin eneeprom=0, this pin is mdc (input): 0 to 25mhz clock, sourced by an external device to sample mdio. sda_mdio 75 i/o pu 4 sda or mdio this pin is tri state when reset#=0. when pin eneeprom=1, this pin becomes sda (input/output) to load the serial eeprom upon reset. then this pin changes to mdio (input/output) after reset. it should be pulled-high by an external resistor. when pin eneeprom=0, this pin is mdio (input/output). it should be pulled-high by an external resistor. 5.8. strapping pins pins that are dual function pins are outputs for led or inputs for strappi ng. below are strapping descriptions only. table 9. strapping pins pin name pin no. type drive (ma) description en_autoxover 69 i pu enable auto crossover function 1: enable auto crossover detection 0: disable auto crossover detection. mdi only en_rst_blnk 71 i pu enable reset blink this enables blinking of the leds upon reset for diagnostic purposes. 1: enable reset led blinking 0: disable reset led blinking distagpri /led_add[4] 91 i/o pu 4 input upon reset = disable 802.1p vlan tag priority based qos function. 1: disable 0: enable output after reset = used for led. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 23 track id: jatr-1076-21 rev. 1.2 pin name pin no. type drive (ma) description disvlan /led_spd[4] 93 i/o pu 4 input upon reset = disable vlan function 1: disable vlan 0: enable vlan. the default vlan membership configuration by internal register is port 4 overlapped with all the other ports, to form 4 individual vlans. this default membership configuration may be modified by setup internal registers via the smi interface or eeprom output after reset = used for led. en48pass1 /led_act[3] 97 i/o pu 4 input upon reset = enable 48 pass 1 1: 48 pass 1, continuously collides 48 input packets then passes 1 packet to retain system resource and avoid the partition in repeater when the packet buffer in 8305sc is full 0: continuously collides to avoid packet loss when the packet buffer in 8305sc is full output after reset = used for led. disarp /led_spd[3] 98 i/o pu 4 input upon reset = disable arp broadcast to all vlans 1: disables ability to broadcast arp broadcast packets to all vlans 0: enables ability to broadcast arp broadcast packets to all vlans arp broadcast frame: did is all f. output after reset = used for led. disleaky /led_add[2] 101 i/o pu 4 input upon reset = disable leaky vlan 1: disable forwarding of unicast frames to other vlans 0: enable forwarding of unicast frames to other vlans broadcast and multicast frames adhere to the vlan configuration. output after reset = used for led. enforward /led_add[0] 111 i/o pu 4 input upon reset = enable to forward 802.1d specified reserved multicast addresses frame 1: forward reserved control frames, with did=01-80-c2-00-00- 02 and 01-80-c2-00-00-04 to 01-80-c2-00-00-0f 0: filter reserved control packet s, with did=01-80-c2-00-00-02 and 01-80-c2-00-00-04 to 01-80-c2-00-00-0f output after reset = used for led. bcindrop /led_act[0] 113 i/o pu 4 input upon reset = broadcast input drop 1: use broadcast input drop mechanism 0: use broadcast output drop mechanism output after reset = used for led. max1536 /led_spd[0] 114 i/o pu 4 input upon reset = maximum frame length 1: 1536 bytes 0: 1552 bytes output after reset = used for led. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 24 track id: jatr-1076-21 rev. 1.2 5.9. port status strapping pins pins that are dual function pins are outputs for leds or inputs for strapping. below are strapping descriptions only. table 10. port status strapping pins pin name pin no. type drive (ma) description setgroup /led_dup[4] 95 i/o pu 4 input upon reset = set group of port 1 1: port 0 is group x. port 1, 2, and 3 are group y 0: port 0, and 1 are group x. port 2, and 3 are group y output after reset = used for led. gxmode /led_add[3] 96 i/o pu 4 input upon reset = group x operating mode 1: utp mode 0: fx mode output after reset = used for led. gymode /led_dup[3] 99 i/o pu 4 input upon reset = group y operating mode 1: utp mode 0: fx mode output after reset = used for led. p4aneg /led_act[2] 103 i/o pu 4 input upon reset = port 4 auto-negotiation ability 1: enable auto-negotiation (nway mode) 0: disable auto-negotiation (force mode) upon reset, this pin sets reg.0.12 of port 4. strap after reset for initial value of port 4 utp mode only. this pin is not used for port 4 fx, mac mode mii, phy mode mii, and phy mode sni. output after reset = used for led. gxaneg /led_spd[2] 104 i/o pu 4 input upon reset = groupx auto-negotiation ability 1: enable auto-negotiation (nway mode) 0: disable auto-negotiation (force mode) upon reset, this pin sets reg.0.12 of group x. strap after reset for initial value of utp mode only. this pin is not used for fx. output after reset = used for led. gyaneg /led_dup[2] 105 i/o pu 4 input upon reset = groupy auto-negotiation ability 1: enable auto-negotiation (nway mode) 0: disable auto-negotiation (force mode) upon reset, this pin sets reg.0.12 of group y. strap after reset for initial value of utp mode only. this pin is not used for fx. output after reset = used for led. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 25 track id: jatr-1076-21 rev. 1.2 pin name pin no. type drive (ma) description gxspd100 /led_add[1] 107 i/o pu 4 input upon reset = group x 10base-t/100base-tx ability gxspd100=1, gxfull=1 => mii reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1 gxspd100=1, gxfull=0 => mii reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1 gxspd100=0, gxfull=1; => mii reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1 gxspd100=0, gxfull=0; => mii reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1 upon reset, this pin sets reg.0.13. in addition, upon reset, this pin and gxfull also sets reg.4.8/4.7/4.6/4.5. strap after reset for initial value of group x utp mode only. this pin is not used for fx. output after reset = used for led. gyspd100 /led_act[1] 108 i/o pu 4 input upon reset = groupy 10base-t/100base-tx ability gyspd100=1, gyfull=1 => mii reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1 gyspd100=1, gyfull=0 => mii reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1 gyspd100=0, gyfull=1; => mii reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1 gyspd100=0, gyfull=0; => mii reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1 upon reset, this pin sets reg.0.13. in addition, upon reset, this pin and gyfull also sets reg.4.8/4.7/4.6/4.5. strap after reset for initial value of group y utp mode only. this pin is not used for fx. output after reset = used for led. gxfull /led_spd[1] 109 i/o pu 4 input upon reset = groupx full duplex ability upon reset, this pin sets the default value of reg.0.8. in addition, on reset, this pin also sets nway full-duplex ability on reg.4.8 and reg.4.6. strap after reset for initial value of group x utp or fx mode. fx can be force 100 full or force 100 half. output after reset = used for led. gyfull /led_dup[1] 110 i/o pu 4 input upon reset = groupy full duplex ability upon reset, this pin sets the default value of reg.0.8. on reset, this pin also sets nway full-duplex ability on reg.4.8 and reg.4.6. strap after reset for initial value of group y utp or fx mode. fx can be force 100 full or force 100 half. output after reset = used for led. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 26 track id: jatr-1076-21 rev. 1.2 5.10. power pins table 11. power pins pin name pin no. type drive (ma) description avdd18 1, 7, 8, 14, 15, 21, 22, 28, 29, 35, 119, 128 p 1.8v analog power hvdd33 118 p 3.3v analog power agnd 4, 11, 18, 25, 32, 122, 126 p analog ground dvdd18 43, 53, 70, 100 p 1.8v digital power dvdd33 62, 87, 106 p 3.3v digital power dgnd 39, 50, 64, 79, 94, 102, 112 p digital ground www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 27 track id: jatr-1076-21 rev. 1.2 6. eeprom description 6.1. port 0 registers 6.1.1. global control register0 table 12. global control register0 name byte.bit description default eeprom existence 0.7 1: eeprom does not exist (pin eneeprom=0 or pin eneeprom=1 but eeprom does not exist) 0: eeprom exists (pin eneeprom=1 and eeprom exists) 0 reserved 0.6 1 internal use 0.5 1 internal use 0.4 1 internal use 0.3 1 enable loop detection function 0.2 1: enable loop detection function 0: disable loop detection function 0 reserved 0.1 1 internal use 0.0 0 6.1.2. global control register1 table 13. global control register1 name byte.bit description default page selection 1.7 1: select the registers in page 1 0: select the registers in page 0 0 reserved 1.6 0 lookup table accessible enable 1.5 1: lookup table is accessible via indirect access registers 0: lookup table is not accessible 0 internal use 1.4 0 reserved 1.3 0 disable 802.1q tag aware vlan 1.2 1: disable 802.1q tagged-vid awar e function. the RTL8305SC will not check the tagged vid on received frames to perform tagged-vid vlan mapping. under this configuration, the RTL8305SC only uses the per port vlan index register to perform port-based vlan mapping 0: enable the member set filtering function of vlan ingress rule. the RTL8305SC checks the tagged vid on received frames with the vida[11:0]~vidh[11:0] to index to a member set, then performs vlan mapping. the RTL8305SC uses tagged-vid vlan mapping for tagged frames but still uses port-based vlan mapping for priority-tagged and untagged frames 1 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 28 track id: jatr-1076-21 rev. 1.2 name byte.bit description default disable vlan member set ingress filtering 1.1 1: the switch will not drop the received frame if the ingress port of this packet is not included in the matched vlan member set. it will still forward the packet to the vlan members specifi ed in the matched member set. this setting works on both port-based and tag-based vlan configurations 0: the switch will drop the received frame if the ingress port of this packet is not included in the matched vlan member set 1 disable vlan tag admit control 1.0 1: the switch accepts all frames it receives whether tagged or untagged. 0: the switch will only accept tagged fra mes and will drop untagged frames. 1 6.1.3. global control register2 table 14. global control register2 name byte.bit description default internal use 2.7 0 internal use 2.6 0 internal use 2.5~2.0 11 1111 6.1.4. global control register3 table 15. global control register3 name byte.bit description default internal use 3.7 0 internal use 3.6 0 internal use 3.5~3.0 11 1111 6.1.5. global control register4 table 16. global control register4 name byte.bit description default reserved 4.7 1 enable defer 4.6 1: enable carrier sense deferring for half duplex back pressure 0: disable carrier sense deferring for half duplex back pressure 1 led blink time 4.5 1: on 43ms, then off 43ms 0: on 120ms, then off 120ms 1 queue weight 4.4~4.3 the frame service ratio between the hi gh priority queue and low priority queue is: 11=16:1 10=always high priority queue first 01=8:1 00=4:1 11 disable broadcast storm control 4.2 1: disable broadcast storm control 0: enable broadcast storm control 1 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 29 track id: jatr-1076-21 rev. 1.2 name byte.bit description default enable power-on blinking 4.1 1: enable power-on led blinking for diagnosis 0: disable power-on led blinking for diagnosis 1 reserved 4.0 1 6.1.6. global control register5 table 17. global control register5 name byte.bit description default reserved 5.7 1 maximum frame length 5.6 1: 1536 byte 0: 1552 byte 1 enable broadcast drop 5.5 1: use broadcast input drop mechanism 0: use broadcast output drop mechanism 1 forward 802.1d reserved mac addresses frame. 5.4 1: forward reserved control frames, which did=01-80-c2-00-00-02 and 01- 80-c2-00-00-04 to 01-80-c2-00-00-0f packets 0: filter reserved control packets, which did=01-80-c2-00-00-02 and 01- 80-c2-00-00-04 to 01-80-c2-00-00-0f 1 disable leaky vlan 5.3 1: disable forwarding of unicast frames to other vlans 0: enable forwarding of unicast frames to other vlans broadcast and multicast frames adhe re to the vlan configuration. 1 disable arp vlan 5.2 1: disable to broadcast the arp broadcast packet to all vlans 0: enable to broadcast the arp broadcast packet to all vlans arp broadcast frame: did is all f. 1 enable 48 pass 1 5.1 1: 48 pass 1, continuously collides 48 input packets then passes 1 packet to retain system resource and avoid partition in the repeater when the packet buffer is full 0: continuously collides to avoid packet loss when the packet buffer is full 1 disable vlan 5.0 1: disable vlan 0: enable vlan. the default vlan membership configuration by internal register is port 4 overlapped with all the other ports, to form 4 individual vlans. this default membership configuration may be modified by setup internal registers via the smi interface or eeprom 1 6.1.7. global control register6 table 18. global control register6 name byte.bit description default reserved 6.7~6.0 1111 1111 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 30 track id: jatr-1076-21 rev. 1.2 6.1.8. global control register7 table 19. global control register 7 name byte.bit description default reserved 7.7~7.6 11 led mode[1:0] 7.5~7.4 11=mode 3: speed, link+act, duplex+col, link/act/speed 10=mode 2: speed, act, duplex/col, bi-color link/activity 01=mode 1: speed, rxact, txact, link 00=mode 0: reserved 11 internal use 7.3 1 disable dual mii interface of port 4 7.2 1: disable dual mii interface of port 4. only provides mi i interface for the mac circuit of port 4 0: enable dual mii interface of port 4. not only provides mii interface for the mac circuit of port 4 but provides mii interface for the phy circuit of port 4 1 reserved 7.1~7.0 11 6.1.9. port 0 control 0 table 20. port 0 control 0 name byte.bit description default reserved 8.7 0 internal use 8.6 1 internal use 8.5~8.4 11 internal use 8.3 1 internal use 8.2 1 vlan tag insert and remove 8.1~8.0 for port 0 egress packets 11=do not insert or remove vlan tags to/from packet 10=insert vlan tags to non-tagged packets 01=remove tag from tagged packets 00=replace the vlan tags for tagged packets and insert a vlan tag to non-tagged packets 11 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 31 track id: jatr-1076-21 rev. 1.2 6.1.10. port 0 control 1 table 21. port 0 control 1 name byte.bit description default reserved 9.7 1 internal use 9.6 0 local loopback 9.5 1: perform ?local loopback?, i.e. loopback mac?s rx back to tx 0: normal operation 0 internal use 9.4 0 discard non pvid packets 9.3 1: if the received packets are tagged, the switch will discard packets whose vid does not match the ingress port?s pvid 0: no packets will be dropped 0 disable 802.1p priority 9.2 1: disable 802.1p priority classification for ingress packets on port 0 0: enable 802.1p priority classification on port 0 1 disable diffserv priority 9.1 1: disable diffserv priority classification for ingress packets on port 0 0: enable diffserv priority classification 1 disable port- based priority on port 0 9.0 1: disable port based priority qos function on port 0 0: enable port based priority qos function on port 0. ingress packets on port 0 will be classed as high priority 1 6.1.11. port 0 control 2 table 22. port 0 control 2 name byte.bit description default reserved 10.7~10.0 0000 0000 6.1.12. port 0 control 3 table 23. port 0 control 3 name byte.bit description default reserved 11.7~11.0 0000 0000 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 32 track id: jatr-1076-21 rev. 1.2 6.1.13. port 0 control 4 & vlan entry [a] table 24. port 0 control 4 & vlan entry [a] name byte.bit description default vlan entry [a] internal use 12.7 1 internal use 12.6 1 reserved 12.5 0 vlan id [a] membership bit [4:0] 12.4~12.0 this 5-bit field specifies which port s are the members of vlan a. if a destination address look up fails, the packet associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 are the members of vlan a 10010 means port 4 and 1 are the members of vlan a 11111 means all 5 ports are the members of vlan a 1 0001 port 0 control 4 port 0 vlan index [3:0] 13.7~13.5 in a port-based vlan configuration, this register indexes port 0?s ?port vlan membership?, which can be defined in one of the registers ?vlan id [a] membership? to ?vlan id [p] membership?. port 0 can only communicate within the memb ership. this register al so indexes to a default port vid (pvid) for each port. the pvid is used in tag insertion and filtering if the tagged vid is not the same as the pvid. 0000 internal use 13.3 1 internal use 13.2 1 internal use 13.1 1 reserved 13.0 0 vlan entry [a] vlan id [a] [7:0] 14.7~14.0 this register along with byte 15.3 ~15.0 defines the ieee 802.1q 12-bit vlan identifier of vlan a 0000 0000 port 0 control 4 & vlan entry [a] internal use 15.7 1 internal use 15.6 1 internal use 15.5 1 internal use 15.4 1 vlan id [a] [11:8] 15.3~15.0 this register along with byte 14.7 ~14.0 defines the ieee 802.1q 12-bit vlan identifier of vlan a 0000 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 33 track id: jatr-1076-21 rev. 1.2 6.2. port 1 registers 6.2.1. internal use register table 25. internal use register name byte.bit description default internal use 16.7~16.0 internal use 0xff internal use 17.7~17.0 internal use 0xff internal use 18.7~18.0 internal use 0xff internal use 19.7~19.0 internal use 0xff internal use 20.7~20.0 internal use 0xff internal use 21.7~21.0 internal use 0xff internal use 22.7~22.0 internal use 0xff internal use 23.7~23.0 internal use 0xff 6.2.2. port 1 control 0 table 26. port 1 control 0 name byte.bit description default reserved 24.7 0 internal use 24.6 1 internal use 24.5~24.4 11 internal use 24.3 1 internal use 24.2 1 vlan tag insert and remove 24.1~24.0 for port 1 egress packets 11=do not insert or remove vlan tags to/from packet 10=insert vlan tags to non-tagged packets 01=remove tag from tagged packets 00=replace the vlan tags for tagged packets and insert a vlan tag to non-tagged packets 11 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 34 track id: jatr-1076-21 rev. 1.2 6.2.3. port 1 control 1 table 27. port 1 control 1 name byte.bit description default reserved 25.7 1 internal use 25.6 0 local loopback 25.5 1: perform local loopback, i.e. loopback mac?s rx back to tx 0: normal operation 0 internal use 25.4 0 discard non pvid packets 25.3 1: if the received packets are tagged, th e switch will discard packets whose vid does not match the ingress port?s pvid 0: no packets will be dropped 0 disable 802.1p priority 25.2 1: disable 802.1p priority classification for ingress packets on port 1 0: enable 802.1p priority classification on port 1 1 disable diffserv priority 25.1 1: disable diffserv priority classification for ingress packets on port 1 0: enable diffserv priority classification 1 disable port- based priority on port 1 25.0 1: disable port based priority qos function on port 1 0: enable port-based priority qos function on port 1. ingress packets on port 1 will be classed as high priority 1 6.2.4. port 1 control 2 table 28. port 1 control 2 name byte.bit description default internal use 26.7 0 reserved 26.6~ 26.5 10 internal use 26.4 1 reserved 26.3~ 26.0 1111 6.2.5. port 1 control 3 table 29. port 1 control 2 name byte.bit description default reserved 27.7 1 internal use 27.6 0 reserved 27.5~ 27.0 00 1111 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 35 track id: jatr-1076-21 rev. 1.2 6.2.6. port 1 control 4 & vlan entry [b] table 30. port 1 control 4 & vlan entry [b] name byte.bit description default vlan entry [b] internal use 28.7 1 internal use 28.6 1 reserved 28.5 0 vlan id [b] membership bit [4:0] 28.4~ 28.0 this 5-bit field specifies which port s are the members of vlan b. if a destination address look up fails, the pa cket associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan b 10010 means port 4 and 1 ar e the members of vlan b 11111 means all 5 ports are members of vlan b. 1 0010 port 1 control 4 port 1 vlan index [3:0] 29.7~ 29.5 in a port-based vlan configuration, this register indexes to port 1?s ?port vlan membership?, which may be defined in one of the registers ?vlan id [a] membership? to ?vlan id [p] memb ership?. port 1 can only communicate with members within this vlan. this register also indexes to a default port vid (pvid) for eac h port. the pvid is used in tag insertion and filtering if the tagged vid is not the same as the pvid. the default value of this register is 000 1, which indexes to the vlan entry [b] that is composed of vlan id [b] membership bit [4:0] in phy1 reg.24.[4:0] and vlan id [b] in phy1 reg.25.[11:0]. 0001 internal use 29.3 1 internal use 29.2 1 internal use 29.1 1 reserved 29.0 0 vlan entry [b] vlan id [b] [7:0] 30.7~ 30.0 this register, along with byte 31.3~31. 0, defines the ieee 802.1q 12-bit vlan identifier of vlan b. 0000 0001 port 1 control 4 & vlan entry [b] internal use 31.7 1 internal use 31.6 1 internal use 31.5 1 internal use 31.4 1 vlan id [b] [11:8] 31.3~ 31.0 this register, along with byte 30.7~30. 0, defines the ieee 802.1q 12-bit vlan identifier of vlan b. 0000 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 36 track id: jatr-1076-21 rev. 1.2 6.3. port 2 registers 6.3.1. internal use register table 31. internal use register name byte.bit description default internal use register internal use 32.7~32.0 0xff internal use 33.7~33.0 0xff internal use 34.7~34.0 0xff internal use 35.7~35.0 0xff internal use 36.7~36.0 0xff internal use 37.7~37.0 0xff internal use 38.7~38.0 0xff internal use 39.7~39.0 0xff 6.3.2. port 2 control 0 table 32. port 2 control 0 name byte.bit description default reserved 40.7 0 internal use 40.6 1 internal use 40.5~40.4 11 internal use 40.3 1 internal use 40.2 1 vlan tag insert and remove 40.1~40.0 for port 2 egress packets 11=do not insert or remove vlan tags to/from packet 10=insert vlan tags to non-tagged packets 01=remove tag from tagged packets 00=replace the vlan tags for tagged packets and insert a vlan tag to non-tagged packets 11 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 37 track id: jatr-1076-21 rev. 1.2 6.3.3. port 2 control 1 table 33. port 2 control 1 name byte.bit description default reserved 41.7 1 internal use 41.6 0 local loopback 41.5 1: perform ?local loopback?, i.e. loopback mac?s rx back to tx 0: normal operation 0 internal use 41.4 0 discard non pvid packets 41.3 1: if the received packets are tagged, the switch will discard packets whose vid does not match the ingress port?s pvid 0: no packets will be dropped 0 disable 802.1p priority 41.2 1: disable 802.1p priority classification for ingress packets on port 2 0: enable 802.1p priority classification on port 2 1 disable diffserv priority 41.1 1: disable diffserv priority classification for ingress packets on port 2 0: enable diffserv priority classification 1 disable port- based priority on port 2 41.0 1: disable port based priority qos function on port 2 0: enable port based priority qos function on port 2. ingress packets on port 2 will be classed as high priority 1 6.3.4. reserved table 34. reserved name byte.bit description default reserved 42.7~42.0 0x20 reserved 43.7~43.0 0x00 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 38 track id: jatr-1076-21 rev. 1.2 6.3.5. port 2 control 2 & vlan entry [c] table 35. port 2 control 2 & vlan entry [c] name byte.bit description default vlan entry [c] internal use 44.7 1 internal use 44.6 1 reserved 44.5 0 vlan id [c] membership bit [4:0] 44.4~44. 0 this 5-bit field specifies which port s are the members of vlan c. if a destination address look up fails, the pa cket associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g. 10001 means port 4 and 0 ar e the members of vlan c 10010 means port 4 and 1 ar e the members of vlan c 11111 means all 5 ports are the members of vlan c 1 0100 port 2 control 2 port 2 vlan index [3:0] 45.7~45. 5 in a port-based vlan configuration, this register indexes to port 2?s ?port vlan membership?, which can be defined in one of the registers ?vlan id [a] membership? to ?vlan id [p] memb ership?. port 2 can only communicate with members within this vlan. this register also indexes to a default port vid (pvid) for eac h port. the pvid is used in tag insertion and filtering if the tagged vid is not the same as the pvid. the default value of this register is 001 0, which indexes to the vlan entry [c] that is composed of vlan id [c] membership bit [4:0] in phy2 reg.24.[4:0] and vlan id [c] in phy2 reg.25.[11:0]. 0010 internal use 45.3 1 internal use 45.2 1 internal use 45.1 1 reserved 45.0 0 vlan entry [c] vlan id [c] [7:0] 46.7~46. 0 this register along with byte 47.3~4 7.0 defines the ieee 802.1q 12-bit vlan identifier of vlan c 0000 0010 port 2 control 2 & vlan entry [c] internal use 47.7 1 internal use 47.6 1 internal use 47.5 1 internal use 47.4 1 vlan id [c] [11:8] 47.3~47. 0 this register along with byte 46.7~4 6.0 defines the ieee 802.1q 12-bit vlan identifier of vlan c 0000 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 39 track id: jatr-1076-21 rev. 1.2 6.4. port 3 registers 6.4.1. switch mac address the switch mac address is used as the sour ce address in mac pause control frames. table 36. switch mac address name byte.bit description default switch mac address [47:40] 48.7~48.0 switch mac address byte 5 0x52 switch mac address [39:32] 49.7~49.0 switch mac address byte 4 0x54 switch mac address [31:24] 50.7~50.0 switch mac address byte 3 0x4c switch mac address [23:16] 51.7~51.0 switch mac address byte 2 0x83 switch mac address [15:8] 52.7~52.0 switch mac address byte 1 0x05 switch mac address [7:0] 53.7~53.0 switch mac address byte 0 0xc0 6.4.2. port 3 control 0 table 37. port 3 control 0 name byte.bit description default reserved 54.7 0 internal use 54.6 1 internal use 54.5~54.4 11 internal use 54.3 1 internal use 54.2 1 vlan tag insert and remove 54.1~54.0 for port 3 egress packets 11=do not insert or remove vlan tags to/from packet 10=insert vlan tags to non-tagged packets 01=remove tag from tagged packets 00=replace the vlan tags for tagged packets and insert a vlan tag to non-tagged packets 11 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 40 track id: jatr-1076-21 rev. 1.2 6.4.3. port 3 control 1 table 38. port 3 control 1 name byte.bit description default reserved 55.7 1 internal use 55.6 0 local loopback 55.5 1: perform ?local loopback?, i.e. loopback mac?s rx back to tx 0: normal operation 0 internal use 55.4 0 discard non pvid packets 55.3 1: if the received packets are tagged, the switch will discard packets whose vid does not match the ingress port?s pvid 0: no packets will be dropped 0 disable 802.1p priority 55.2 1: disable 802.1p priority classification for ingress packets on port 3 0: enable 802.1p priority classification on port 3 1 disable diffserv priority 55.1 1: disable diffserv priority classification for ingress packets on port 3 0: enable diffserv priority classification 1 disable port-based priority on port 3 55.0 1: disable port-based priority qos function on port 3 0: enable port-based priority qos function on port 3. ingress packets on port 3 will be classed as high priority 1 6.4.4. reserved table 39. reserved name byte.bit description default reserved 56.7~56.0 0x00 reserved 57.7~57.0 0x00 6.4.5. port 3 control 2 & vlan entry [d] table 40. port 3 control 2 & vlan entry [d] name byte.bit description default vlan entry [d] internal use 58.7 1 internal use 58.6 1 reserved 58.5 0 vlan id [d] membership bit [4:0] 58.4~58.0 this 5-bit field specifies which port s are the members of vlan d. if a destination address look up fails, the packet associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan d 10010 means port 4 and 1 ar e the members of vlan d 11111 means all 5 ports are the members of vlan d 1 1000 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 41 track id: jatr-1076-21 rev. 1.2 port 3 control 2 port 3 vlan index [3:0] 59.7~59.5 in a port-based vlan configuration, this register indexes to port 3?s ?port vlan membership?, which can be defined in one of the registers ?vlan id [a] membership? to ?vlan id [p] membership?. port 3 can only communicate with the members within this vlan. this register also indexes to a default port vid (pvid) for each port. the pvid is used in tag insertion and filtering if the tagg ed vid is not the same as the pvid. the default value of this register is 0011, which indexes to the vlan entry [d] that is composed of vlan id [d] membership bit [4:0] in phy3 reg.24.[4:0] and vlan id [d] in phy3 reg.25.[11:0]. 0011 internal use 59.3 1 internal use 59.2 1 internal use 59.1 1 reserved 59.0 0 vlan entry [d] vlan id [d] [7:0] 60.7~60.0 this register along with byte 61.3 ~61.0 defines the ieee 802.1q 12-bit vlan identifier of vlan d 0000 0011 port 3 control 2 & vlan entry [d] internal use 61.7 1 internal use 61.6 1 internal use 61.5 1 internal use 61.4 1 vlan id [d] [11:8] 61.3~61.0 this register along with byte 60.7 ~60.0 defines the ieee 802.1q 12-bit vlan identifier of vlan d 0000 6.4.6. internal use register table 41. internal use register name byte.bit description default internal use 62.7~62.0 0x00 internal use 63.7~63.0 0x00 internal use 64.7~64.0 0x00 internal use 65.7~65.0 0x00 internal use 66.7~66.0 0x00 internal use 67.7~67.0 0x00 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 42 track id: jatr-1076-21 rev. 1.2 6.5. port 4 registers 6.5.1. port 4 control 0 table 42. port 4 control 0 name byte.bit description default reserved 68.7 0 internal use 68.6 1 internal use 68.5~68.4 11 internal use 68.3 1 internal use 68.2 1 vlan tag insert and remove 68.1~68.0 for port 4 egress packets 11=do not insert or remove vlan tags to/from packet 10=insert vlan tags to non-tagged packets 01=remove tag from tagged packets 00=replace the vlan tags for tagged packets and insert a vlan tag to non-tagged packets 11 6.5.2. port 4 control 1 table 43. port 4 control 1 name byte.bit description default reserved 69.7 1 internal use 69.6 0 local loopback 69.5 1: perform ?local loopback?, i.e. loopback mac?s rx back to tx 0: normal operation 0 internal use 69.4 0 discard non pvid packets 69.3 1: if the received packets are tagged, the switch will discard packets whose vid does not match the ingress port?s pvid 0: no packets will be dropped 0 disable 802.1p priority 69.2 1: disable 802.1p priority classification for ingress packets on port 4 0: enable 802.1p priority classification on port 4 1 disable diffserv priority 69.1 1: disable diffserv priority classification for ingress packets on port 4 0: enable diffserv priority classification 1 disable port- based priority on port 4 69.0 1: disable port based priority qos function on port 4 0: enable port based priority qos function on port 4. ingress packet on port 4 will be classified as high priority 1 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 43 track id: jatr-1076-21 rev. 1.2 6.5.3. reserved table 44. reserved name byte.bit description default reserved 70.7~70.0 0x00 reserved 71.7~71.0 0x00 6.5.4. port 4 control 2 & vlan entry [e] table 45. port 4 control 2 & vlan entry [e] name byte.bit description default vlan entry [e] internal use 72.7 1 internal use 72.6 1 reserved 72.5 0 vlan id [e] membership bit [4:0] 72.4~72.0 this 5-bit field specifies which port s are the members of vlan e. if a destination address look up fails, a p acket associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan e 10010 means port 4 and 1 ar e the members of vlan e 11111 means all 5 ports are the members of vlan e 1 1111 port 4 control 2 port 4 vlan index [3:0] 73.7~73.5 in a port-based vlan configuration, this register indexes to port 4?s ?port vlan membership?, which can be defined in one of the registers ?vlan id [a] membership? to ?vlan id [p] membership?. port 4 can only communicate with the members within this vlan. this register also indexes to a default port vid (pvid) for each port. the pvid is used in tag insertion and filtering if the tagg ed vid is not the same as the pvid. the default value of this register is 0100, which indexes to the vlan entry [e] that is composed of vlan id [e] membership bit [4:0] in phy4 reg.24.[4:0] and vlan id [e] in phy4 reg.25.[11:0]. 0100 internal use 73.3 1 internal use 73.2 1 internal use 73.1 1 reserved 73.0 0 vlan entry [e] vlan id [e] [7:0] 74.7~74.0 this register, along with byte 75.3 ~75.0, defines the ieee 802.1q 12-bit vlan identifier of vlan e 0000 0100 port 4 control 2 & vlan entry [e] internal use 75.7 1 internal use 75.6 1 internal use 75.5 1 internal use 75.4 1 vlan id [e] [11:8] 75.3~75.0 this register, along with byte 74.7 ~74.0, defines the ieee 802.1q 12-bit vlan identifier of vlan e 0000 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 44 track id: jatr-1076-21 rev. 1.2 6.5.5. internal use register table 46. internal use register name byte.bit description default reserved 76.7 0 internal use 76.6~76.4 100 reserved 76.3 0 internal use 76.2~76.0 000 6.5.6. 802.1p base priority table 47. 802.1p base priority name byte.bit description default 802.1p base priority 77.7~77.5 classifies priority for incoming 802.1q packets, if 802.1p priority classification is enabled. ?user prio rity? compared against this value. >=: classify as high priority <: classify as low priority 100 reserved 77.4~77.0 0 0000 6.6. vlan entries 6.6.1. vlan entry [f] table 48. vlan entry [f] name byte.bit description default vlan entry [f] reserved 78.7~78.5 000 vlan id [f] membership bit [4:0] 78.4~78.0 this 5-bit field specifies which port s are the members of vlan f. if a destination address look up fails, pack ets associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan f 10010 means port 4 and 1 ar e the members of vlan f 11111 means all 5 ports are the members of vlan f 1 0001 reserved 79.7~79.0 0101 0000 vlan id [f] [7:0] 80.7~80.0 this register along with byte 81.3 ~81.0 defines the ieee 802.1q 12-bit vlan identifier of vlan f 0000 0101 reserved 81.7~81.4 1111 vlan id [f] [11:8] 81.3~81.0 this register along with byte 80.7 ~80.0 defines the ieee 802.1q 12-bit vlan identifier of vlan f 0000 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 45 track id: jatr-1076-21 rev. 1.2 6.6.2. vlan entry [g] table 49. vlan entry [g] name byte.bit description default vlan entry [g] reserved 82.7~82.5 000 vlan id [g] membership bit [4:0] 82.4~82.0 this 5-bit field specifies which port s are the members of vlan g. if a destination address look up fails, pack ets associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan g 10010 means port 4 and 1 ar e the members of vlan g 11111 means all 5 ports are the members of vlan g 1 0010 reserved 83.7~83.0 0110 0000 vlan id [g] [7:0] 84.7~84.0 this register along with byte 85.3 ~85.0 defines the ieee 802.1q 12-bit vlan identifier of vlan g 0000 0110 reserved 85.7~85.4 1111 vlan id [g] [11:8] 85.3~85.0 this register along with byte 84.7 ~84.0 defines the ieee 802.1q 12-bit vlan identifier of vlan g 0000 6.6.3. vlan entry [h] table 50. vlan entry [h] name byte.bit description default vlan entry [h] reserved 86.7~86.5 000 vlan id [h] membership bit [4:0] 86.4~86.0 this 5-bit field specifies which port s are the members of vlan h. if a destination address look up fails, pack ets associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan h 10010 means port 4 and 1 ar e the members of vlan h 11111 means all 5 ports are members of vlan h 1 0100 reserved 87.7~87.0 0111 0000 vlan id [h] [7:0] 88.7~88.0 this register along with byte 89.3~8 9.0 defines the ieee 802.1q 12-bit vlan identifier of vlan h 0000 0111 reserved 89.7~89.4 1111 vlan id [h] [11:8] 89.3~89.0 this register along with byte 88.7~8 8.0 defines the ieee 802.1q 12-bit vlan identifier of vlan h 0000 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 46 track id: jatr-1076-21 rev. 1.2 6.6.4. vlan entry [i] table 51. vlan entry [i] name byte.bit description default vlan entry [i] reserved 90.7~90.5 000 vlan id [i] membership bit [4:0] 90.4~90.0 this 5-bit field specifies which port s are the members of vlan i. if a destination address look up fails, pack ets associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan i 10010 means port 4 and 1 ar e the members of vlan i 11111 means all 5 ports are the members of vlan i 1 1000 reserved 91.7~91.0 1000 0000 vlan id [i] [7:0] 92.7~92.0 this register along with byte 93.3~9 3.0 defines the ieee 802.1q 12-bit vlan identifier of vlan i 0000 1000 reserved 93.7~93.4 1111 vlan id [i] [11:8] 93.3~93.0 this register along with byte 92.7~9 2.0 defines the ieee 802.1q 12-bit vlan identifier of vlan i 0000 6.6.5. vlan entry [j] table 52. vlan entry [j] name byte.bit description default vlan entry [i] reserved 94.7~94.5 000 vlan id [j] membership bit [4:0] 94.4~94.0 this 5-bit field specifies which port s are the members of vlan j. if a destination address look up fails, pack ets associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan j 10010 means port 4 and 1 ar e the members of vlan j 11111 means all 5 ports are members of vlan j 1 1111 reserved 95.7~95.0 1001 0000 vlan id [j] [7:0] 96.7~96.0 this register along with byte 97.3~9 7.0 defines the ieee 802.1q 12-bit vlan identifier of vlan j 0000 1001 reserved 97.7~97.4 1111 vlan id [j] [11:8] 97.3~97.0 this register along with byte 96.7~9 6.0 defines the ieee 802.1q 12-bit vlan identifier of vlan j 0000 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 47 track id: jatr-1076-21 rev. 1.2 6.6.6. vlan entry [k] table 53. vlan entry [k] name byte.bit description default reserved 98.7~98.5 000 vlan id [k] membership bit [4:0] 98.4~98.0 this 5-bit field specifies which port s are the members of vlan k. if a destination address look up fails, the pa cket associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan k 10010 means port 4 and 1 ar e the members of vlan k 11111 means all 5 ports are the members of vlan k 1 0001 reserved 99.7~99.0 1010 0000 vlan id [k] [7:0] 100.7~100. 0 this register along with byte 101.3~101.0 defines the ieee 802.1q 12-bit vlan identifier of vlan k 0000 1010 reserved 101.7~101. 4 1111 vlan id [k] [11:8] 101.3~101. 0 this register along with byte 100.7~100.0 defines the ieee 802.1q 12-bit vlan identifier of vlan k 0000 6.6.7. vlan entry [l] table 54. vlan entry [l] name byte.bit description default vlan entry [l] reserved 102.7~102.5 000 vlan id [l] membership bit [4:0] 102.4~102.0 this 5-bit field specifies which port s are the members of vlan l. if a destination address look up fails, pack ets associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan l 10010 means port 4 and 1 ar e the members of vlan l 11111 means all 5 ports are members of vlan l 1 0010 reserved 103.7~103.0 1011 0000 vlan id [l] [7:0] 104.7~104.0 this register along with byte 105.3~105.0 defines the ieee 802.1q 12-bit vlan identifier of vlan l 0000 1011 reserved 105.7~105.4 1111 vlan id [l] [11:8] 105.3~105.0 this register along with byte 104.7~104.0 defines the ieee 802.1q 12-bit vlan identifier of vlan l 0000 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 48 track id: jatr-1076-21 rev. 1.2 6.6.8. vlan entry [m] table 55. vlan entry [m] name byte.bit description default vlan entry [m] reserved 106.7~106.5 000 vlan id [m] membership bit [4:0] 106.4~106.0 this 5-bit field specifies which port s are the members of vlan m. if a destination address look up fails, the packet associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan m 10010 means port 4 and 1 ar e the members of vlan m 11111 means all 5 ports are members of vlan m 1 0100 reserved 107.7~107.0 1100 0000 vlan id [m] [7:0] 108.7~108.0 this register along with byte 109.3~109.0 defines the ieee 802.1q 12-bit vlan identifier of vlan m 0000 1100 reserved 109.7~109.4 1111 vlan id [m] [11:8] 109.3~109.0 this register along with byte 108.7~108.0 defines the ieee 802.1q 12-bit vlan identifier of vlan m 0000 6.6.9. vlan entry [n] table 56. vlan entry [n] name byte.bit description default vlan entry [n] reserved 110.7~110.5 000 vlan id [n] membership bit [4:0] 110.4~110.0 this 5-bit field specifies which port s are the members of vlan n. if a destination address look up fails, pack ets associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan n 10010 means port 4 and 1 ar e the members of vlan n 11111 means all 5 ports are the members of vlan n 1 1000 reserved 111.7~111.0 1101 0000 vlan id [n] [7:0] 112.7~112.0 this register along with byte 113.3~113.0 defines the ieee 802.1q 12-bit vlan identifier of vlan n 0000 1101 reserved 113.7~113.4 1111 vlan id [n] [11:8] 113.3~113.0 this register along with byte 112.7~112.0 defines the ieee 802.1q 12-bit vlan identifier of vlan m 0000 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 49 track id: jatr-1076-21 rev. 1.2 6.6.10. vlan entry [o] table 57. vlan entry [o] name byte.bit description default vlan entry [o] reserved 114.7~114.5 000 vlan id [o] membership bit [4:0] 114.4~114.0 this 5-bit field specifies which port s are the members of vlan o. if a destination address look up fails, pack ets associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan o 10010 means port 4 and 1 ar e the members of vlan o 11111 means all 5 ports are members of vlan o 1 1111 reserved 115.7~115.0 1110 0000 vlan id [o] [7:0] 116.7~116.0 this register along with byte 117.3~117.0 defines the ieee 802.1q 12-bit vlan identifier of vlan o 0000 1110 reserved 117.7~117.4 1111 vlan id [o] [11:8] 117.3~117.0 this register along with byte 116.7~116.0 defines the ieee 802.1q 12-bit vlan identifier of vlan o 0000 6.6.11. vlan entry [p] table 58. vlan entry [p] name byte.bit description default vlan entry [p] reserved 118.7~118.5 000 vlan id [p] membership bit [4:0] 118.4~118.0 this 5-bit field specifies which port s are the members of vlan p. if a destination address look up fails, pack ets associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan p 10010 means port 4 and 1 ar e the members of vlan p 11111 means all 5 ports are members of vlan p 1 0001 reserved 119.7~119.0 1111 0000 vlan id [p] [7:0] 120.7~120.0 this register along with byte 27.3 ~27.0 defines the ieee 802.1q 12-bit vlan identifier of vlan p 0000 1111 reserved 121.7~121.4 1111 vlan id [p] [11:8] 121.3~121.0 this register along with byte 26.7 ~26.0 defines the ieee 802.1q 12-bit vlan identifier of vlan p 0000 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 50 track id: jatr-1076-21 rev. 1.2 7. register descriptions hardware reset: pin reset#=0 to 1. reset all th en load eeprom and pin registers with serial eeprom and pin strapping. soft reset: write bit12 of reg16 of phy0 as 1. reset all except loading eeprom and pin registers with serial eeprom and pins. after updating the eepro m or pin registers via smi, the external device must do a soft reset in order to allow th e configuration change to take affect. note: in this section the following abbreviations are used: ro: read only lh: latch high until clear rw: read/write sc: self clearing ll: latch low until clear table 59. register descriptions name phy page register register description 0 control register 1 status register 2 phy identifier 1 3 phy identifier 2 4 auto-negotiation advertisement register 5 auto-negotiation link partner ability register 6 auto-negotiation expansion register 16~19 global control register 22 port 0 control register 0 24 port 0 control register 1 & vlan id [a] membership 0 25 port 0 control register 2 & vlan id [a] 0 26 reserved 1 26 vlan id [f] membership 0 27 reserved 1 27 vlan id [f] 0 28 reserved 1 28 vlan id [k] membership 0 29 reserved 1 29 vlan id [k] 0 30 reserved 1 30 vlan id [p] membership 0 31 reserved port 0 phy register 0 1 31 vlan id [p] 0 control register 1 status register 2 phy identifier 1 port 1 phy register 1 0 3 phy identifier 2 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 51 track id: jatr-1076-21 rev. 1.2 name phy page register register description 4 auto-negotiation advertisement register 5 auto-negotiation link partner ability register 6 auto-negotiation expansion register 16~17 internal use register 18~19 internal use register 22 port 1 control register 0 23 global option register 0 24 port 1 control register 1 & vlan id[b] membership 25 port 1 control register 2 & vlan id[b] 0 26 reserved 1 26 vlan id [g] membership 0 27 reserved 1 27 vlan id [g] 0 28 reserved 1 28 vlan id [l] membership 0 29 reserved 1 29 vlan id [l] 0 control register 1 status register 2 phy identifier 1 3 phy identifier 2 4 auto-negotiation advertisement register 5 auto-negotiation link partner ability register 6 auto-negotiation expansion register 16~17 internal use register 18~19 internal use register 22 port 2 control register 0 24 port 2 control register 1 & vlan id[c] membership 0 25 port 2 control register 2 & vlan id [c] 0 26 reserved 1 26 vlan id [h] membership 0 27 reserved 1 27 vlan id [h] 0 28 reserved 1 28 vlan id [m] membership 0 29 reserved port 2 phy register 2 1 29 vlan id [m] 0 control register 1 status register 2 phy identifier 1 3 phy identifier 2 4 auto-negotiation advertisement register 5 auto-negotiation link partner ability register port 3 phy register 3 0 6 auto-negotiation expansion register www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 52 track id: jatr-1076-21 rev. 1.2 name phy page register register description 16~18 switch mac address 19~21 internal use register 22 port 3 control register 0 24 port 3 control register 1 & vlan id[d] membership 25 port 3 control register 2 & vlan id [d] 0 26 reserved 1 26 vlan id [i] membership 0 27 reserved 1 27 vlan id [i] 0 28 reserved 1 28 vlan id [n] membership 0 29 reserved 1 29 vlan id [n] 0 control register 1 status register 2 phy identifier 1 3 phy identifier 2 4 auto-negotiation advertisement register 5 auto-negotiation link partner ability register 6 auto-negotiation expansion register 16 indirect access control 17~20 indirect access data 21 internal use register 22 port 4 control register 0 24 port 4 control register 1 & vlan id[e] membership 0 25 port 4 control register 2 & vlan id [e] 0 26 reserved 1 26 vlan id [j] membership 0 27 reserved 1 27 vlan id [j] 0 28 reserved 1 28 vlan id [o] membership 0 29 reserved port 4 phy register 4 1 29 vlan id [o] 0 control register 1 status register 2 phy identifier 1 3 phy identifier 2 phy register for port 4 mac 5 0 4 auto-negotiation advertisement register www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 53 track id: jatr-1076-21 rev. 1.2 7.1. phy 0 registers 7.1.1. phy 0 register 0 for port 0: control table 60. phy 0 register 0: control reg.bit name mode description default 0.15 reset rw/sc 1: phy reset. this bit is self-clearing 0 0.14 loopback (digital loopback) rw 1: enable loopback. this will loopback txd to rxd and ignore all activity on the cable media 0: normal operation this function is usable only when this phy is operated in 10base-t full duplex or 100base-tx full duplex. 0 0.13 speed select rw 1: 100mbps 0: 10mbps when nway is enabled, this bit reflects the result of auto- negotiation (read only). when nway is disabled, this bit can be set through smi. (read/write). when 100fx mode is enabled, this bit=1 (read only). from pin 0.12 auto negotiation enable rw 1: enable auto-negotiation process 0: disable auto-negotiation process this bit can be set through smi (read/write). when 100fx mode is enabled, this bit=0 (read only). 100fx must be in force mode. in order to avoid errors, the RTL8305SC will ignore the action of this bit when writing reg0.12 as 1 in 100fx mode. from pin 0.11 power down rw 1: power down. all functions will be disabled except smi function 0: normal operation 0 0.10 isolate rw 1: electrically isolates the phy from mii. phy is still able to respond to mdc/mdio 0: normal operation 0 0.9 restart auto negotiation rw/sc 1: restart auto-negotiation process 0: normal operation 0 0.8 duplex mode rw 1: full duplex operation 0: half duplex operation when nway is enabled (reg0.12=1), this bit reflects the result of auto-negotiation (read only). when nway is disabled (reg0.12=0, force mode of utp or 100fx), this bit can be set through smi (read/write). 100fx must be in force mode. in order to avoid errors, the RTL8305SC will ignore the action to this bit when writing reg0.12 as 1 in 100fx mode. from pin 0.[7:0] reserved 0000 0000 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 54 track id: jatr-1076-21 rev. 1.2 7.1.2. phy 0 register 1 for port 0: status table 61. phy 0 register 1: status reg.bit name mode description default 1.15 100base_t4 ro 0: no 100base-t4 capability 0 1.14 100base_tx_fd ro 1: 100base-tx full duplex capable 0: not 100base-tx full duplex capable 1 1.13 100base_tx_hd ro 1: 100base-tx half duplex capable 0: not 100base-tx half duplex capable 1 1.12 10base_t_fd ro 1: 10base-tx full duplex capable 0: not 10base-tx full duplex capable 1 1.11 10base_t_hd ro 1: 10base-tx half duplex capable 0: not 10base-tx half duplex capable 1 1.[10:7] reserved ro 0000 1.6 mf preamble suppression ro the RTL8305SC will accept ma nagement frames with preamble suppressed. (the RTL8305SC accepts management frames without preamble. minimum preamble of 32 bits is required for the first smi read/write transaction after reset. one idle bit is required between any two management transactions as defined in ieee 802.3u). 1 1.5 auto-negotiate complete ro 1: auto-negotiation process completed. mii reg.4 and 5 are valid if this bit is set 0: auto-negotiation process not completed 0 1.4 remote fault ro/lh 1: remote fault condition detected 0: no remote fault when in 100fx mode, this bit means in-band signal far-end- fault is detected 0 1.3 auto-negotiation ability ro 1: nway auto-negotiation capable (permanently=1) 1 1.2 link status ro/ll 1: link is established. if the link fails, this bit will be 0 until after reading this bit again 0: link has failed 0 1.1 jabber detect ro/lh 0: no jabber detected the RTL8305SC does not support this function. 0 1.0 extended capability ro 1: extended register capable (permanently=1) 1 7.1.3. phy 0 register 2 for port 0: phy identifier 1 table 62. phy 0 register 2: phy identifier 1 reg.bit name mode description default 2.[15:0] oui ro composed of the 3 rd to 18 th bits of the organizationally unique identifier (oui), respectively 0x001c www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 55 track id: jatr-1076-21 rev. 1.2 7.1.4. phy 0 register 3 for port 0: phy identifier 2 table 63. phy 0 register 3: phy identifier 2 reg.bit name mode description default 3.[15:10] oui ro assigned to the 19 th through 24 th bits of the oui 110010 3.[9:4] model number ro manufacturer?s model number (05: indicates rtl8305 000101 3.[3:0] revision number ro manufacturer?s revision number (02: indicates sc 0010 7.1.5. phy 0 register 4 for port 0: auto-negotiation advertisement note: each time the link ability of the RTL8305SC is reconfigured, th e auto-negotiation process should be executed to allow the configuration to take effect. table 64. phy 0 register 4: auto-negotiation advertisement reg.bit name mode description default 4.15 next page ro 1: next page enabled 0: next page disabled (permanently=0) 0 4.14 acknowledge ro permanently=0 0 4.13 remote fault rw 1: advertises that the RTL8305SC has detected a remote fault 0: no remote fault detected 0 4.[12:11] reserved ro 00 4.10 pause rw 1: advertises that the RTL8305SC possesses 802.3x flow control capability 0: no flow control capability from pin 4.9 100base-t4 ro technology not supported. (permanently=0) 0 4.8 100base-tx-fd rw 1: 100base-tx full duplex capable 0: not 100base-tx full duplex capable from pin 4.7 100base-tx rw 1: 100base-tx half duplex capable 0: not 100base-tx half duplex capable from pin 4.6 10base-t-fd rw 1: 10base-tx full duplex capable 0: not 10base-tx full duplex capable from pin 4.5 10base-t rw 1: 10base-tx half duplex capable 0: not 10base-tx half duplex capable 1 4.[4:0] selector field rw [00001]=ieee 802.3 00001 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 56 track id: jatr-1076-21 rev. 1.2 7.1.6. phy 0 register 5 for port 0: auto-negotiation link partner ability table 65. phy 0 register 5: auto -negotiation link partner ability reg.bit name mode description default 5.15 next page ro 1: link partner desires next page transfer 0: link partner does not desire next page transfer 0 5.14 acknowledge ro 1: link partner acknowledges rece ption of fast link pulse (flp) words 0: not acknowledged by link partner 0 5.13 remote fault ro 1: remote fault indicated by link partner 0: no remote fault indicated by link partner 0 5.[12:11] reserved ro 00 5.10 pause ro 1: flow control supported by link partner 0: flow control not supported by link partner 0 5.9 100base-t4 ro 1: 100base-t4 supported by link partner 0: 100base-t4 not supported by link partner 0 5.8 100base-tx-fd ro 1: 100base-tx full duplex supported by link partner 0: 100base-tx full duplex not supported by link partner for 100fx mode, this bit will be set if reg.0.8=1 or full=1 after link is established when auto negotiation is disabled, this bit will be set if reg0.13=1 and reg0.8=1 after link is established. 0 5.7 100base-tx ro 1: 100base-tx half duplex supported by link partner 0: 100base-tx half duplex not supported by link partner for 100fx mode, this bit is set when reg.0.8=1 or full=1 after link established. when auto negotiation is disabled, this bit will be set if reg0.13=1 and reg0.8=0 after link is established. 0 5.6 10base-t-fd ro 1: 10base-tx full duplex supported by link partner 0: 10base-tx full duplex not supported by link partner when auto negotiation is disabled, this bit will be set if reg0.13=0 and reg0.8=1 after link is established. 0 5.5 10base-t ro 1: 10base-tx half duplex supported by link partner 0: 10base-tx half duplex not supported by link partner when auto negotiation is disabled, this bit will be set if reg0.13=0 and reg0.8=0 after link is established. 0 5.[4:0] selector field ro [00001]=ieee 802.3 00001 7.1.7. phy 0 register 16: global control 0 table 66. phy 0 register 16: global control 0 reg.bit name mode description default 16.15 page selection rw 1: select the registers in page 1 0: select the registers in page 0 0 16.14 reserved 0 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 57 track id: jatr-1076-21 rev. 1.2 reg.bit name mode description default 16.13 lookup table accessible enable rw 1: lookup table is accessible via indirect access registers 0: lookup table is not accessible 0 16.12 software reset rw sc 1: soft reset. this bit is self-clearing if this bit is set to 1, the RTL8305SC will reset all internal registers except phy registers, and will not load configurations from eeprom or strapping pins. software reset is designed to provide a convenient way for users to change the configuration via smi. after changing regist er values in the RTL8305SC (except phy registers) via smi, the external device must execute a soft reset (by setting this bit to 1) in order to update the configuration. 0 16.11 reserved 0 16.10 disable 802.1q tag aware vlan rw 1: disable 802.1q tagged-vid aware function. the RTL8305SC will not check the ta gged vid on received frames to perform tagged-vid vlan mapping. under this configuration, the RTL8305SC only uses the per-port vlan index register to perform port-based vlan mapping 0: enable the member set filtering function of the vlan ingress rules. the RTL8305SC checks the tagged vid on received frames with the vida[1 1:0]~vidh[11:0] to index to a member set, then performs vlan mapping. the RTL8305SC uses tagged-vid vlan mapping for tagged frames but still uses port-based vlan mapping for priority-tagged and untagged frames 1 16.9 disable vlan member set ingress filtering rw 1: the switch will not drop the r eceived frame if the ingress port of this packet is not included in the matched vlan member set. it will still forward the packet to the vlan members specified in the matched member set. this setting both works on port- based and tag-based vlan configurations 0: the switch will drop the received frame if the ingress port of this packet is not included in the matched vlan member set 1 16.8 disable vlan tag admit control rw 1: the switch accepts all frames it receives whether tagged or untagged 0: the switch will only accept tagged frames and will drop untagged frames 1 16.7 eeprom existence ro 1: eeprom does not exist (pin eneeprom=0 or pin eneeprom=1 but eeprom does not exist) 0: eeprom exists (pin eneeprom=1 and eeprom exists) 1 16.6 internal use rw 1 16.5 internal use rw 1 16.4 internal use rw 1 16.3 internal use rw 1 16.2 enable loop detection function rw 1: enable loop detection function 0: disable loop detection function 0 16.1 reserved rw 1 16.0 internal use rw 0 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 58 track id: jatr-1076-21 rev. 1.2 7.1.8. phy 0 register 17: global control 1 table 67. phy 0 register 17: global control 1 reg.bit name mode description default 17.15 internal use rw 0 17.14 internal use rw 0 17.[13:8] internal use rw 11 1111 17.7 internal use rw 0 17.6 internal use rw 0 17.[5:0] internal use rw 11 1111 7.1.9. phy 0 register 18: global control 2 table 68. phy 0 register 18: global control 2 reg.bit name mode description default 18.15 reserved rw default=1 18.14 maximum frame length rw 1: 1536bytes 0: 1552bytes pin max1536 strap option default=1 18.13 enable broadcast drop rw 1: use broadcast input drop mechanism 0: use broadcast output drop mechanism pin bcindrop strap option default=1 18.12 forward 802.1d reserved mac addresses frame. rw 1: forward reserved control frames, whose did=01-80-c2-00- 00-02 and 01-80-c2-00-00-04 to 01-80-c2-00-00-0f packets 0: filter reserved control packets, whose did=01-80-c2-00- 00-02 and 01-80-c2-00-00-04 to 01-80-c2-00-00-0f pin enforward strap option default=1 18.11 disable leaky vlan rw 1: disable forwarding of unicast frames to other vlans 0: enable forwarding of unicast frames to other vlans broadcast and multicast frames adhere to the vlan configuration pin disleaky strap option default=1 18.10 disable arp vlan rw 1: disable broadcasting of arp broadcast packets to all vlans 0: enable broadcasting of arp broadcast packets to all vlans arp broadcast frame did is all f pin disarp strap option default=1 18.9 enable 48 pass 1 rw 1: 48 pass 1. continuously collides 48 input packets then passes 1 packet to retain system resources and avoid partition in the repeater when th e packet buffer is full 0: continuously collides to avoid packet loss when the packet buffer is full pin en48pass1 strap option default=1 18.8 disable vlan rw 1: disable vlan 0: enable vlan. the default vlan membership configuration by internal register is port 4 overlapped with all the other ports, to form 4 individual vlans. this default membership configuration may be modified by setting up internal registers via the smi interface or eeprom pin disvlan strap option default=1 18.7 reserved rw default=1 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 59 track id: jatr-1076-21 rev. 1.2 reg.bit name mode description default 18.6 enable defer rw 1: enable carrier sense deferring for half duplex back pressure 0: disable carrier sense deferring for half duplex back pressure pin endefer strap option default=1 18.5 led blink time rw 1: on for 43ms, then off for 43ms 0: on for 120ms, then off for 120ms pin led_blnk_ time strap option default=1 18.[4:3] queue weight rw the frame service ratio between the high priority queue and low priority queue is: 11=16:1 10=always high priority queue first 01=8:1 00=4:1 pin qweight[1:0] strap option default=11 18.2 disable broadcast storm control rw 1: disable broadcast storm control 0: enable broadcast storm control pin disbrdctrl strap option default=1 18.1 enable power-on blinking rw 1: enable power-on led blinking for diagnosis 0: disable power-on led blinking for diagnosis pin en_rst_blnk strap option default=1 18.0 reserved 1 7.1.10. phy 0 register 19: global control 3 table 69. phy 0 register 19: global control 3 reg.bit name mode description default 19.[15:14 ] reserved 11 19.[13:12 ] led mode[1:0] rw 11=mode 3: speed, link+act, duplex+col, link/act/speed 10=mode 2: speed, act, duplex/col, bi-color link/activity 01=mode 1: speed, rxact, txact, link 00=mode 0: reserved pin ledmode[1:0] strap option default=11 19.11 internal use rw default=1 19.10 disable dual mii interface of port 4 rw 1: disable dual mii interface of port 4. only provides mii interface for the mac circuit of port 4 0: enable dual mii interface of port 4. provides mii interface for the mac circuit of port 4, and also provides mii interface for the phy circuit of port 4 pin disdualmii strap option default=1 19.[9:0] reserved 11 1111 1111 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 60 track id: jatr-1076-21 rev. 1.2 7.1.11. phy 0 register 22: port 0 control register 0 table 70. phy 0 register 22: port 0 control register 0 reg.bit name mode description default 22.15 reserved 1 22.14 internal use rw 0 22.13 port 0 local loopback rw 1: perform ?local loopback?, i.e. loop mac?s rx back to tx. 0: normal operation 0 22.12 internal use rw 0 22.11 port 0 non pvid packets discard rw 1: if the received packets are tagged, the switch will discard packets whose vid does not match the ingress port default vid, which is indexed by port 0?s ?port based vlan index? 0: no packets will be discarded 0 22.10 port 0 802.1p priority disable rw 1: disable 802.1p priority classification for ingress packets on port 0 0: enable 802.1p priority classification pin distagpri strap option default=1 22.9 port 0 diffserv priority disable rw 1: disable diffserv priority cla ssification for ingress packets on port 0 0: enable diffserv priority classification pin disdspri strap option default=1 22.8 port 0 port-based priority disable rw 1: disable port-based priority qos function on port 0 0: enable port-based priority qos function on port 0. ingress packet on port 0 will be classified as high priority pin disportpri[0] strap option default=1 22.7 reserved 0 22.6 internal use rw 1 22.[5:4] internal use rw 1 22.3 internal use rw 1 22.2 internal use rw 1 22.[1:0] port 0 vlan tag insert and remove rw 11=do not insert or remove vlan tags to/from packets that are output on this port 10=the switch will add vlan tags to packets, if they are not tagged when these packets are output on this port. the switch will not add tags to packets already tagged. the inserted tag is the ingress port?s ?default tag?, which is indexed by port 0?s ?port based vlan index? 01=the switch will remove vlan tags from packets if they are tagged when these packets are output on port 0. the switch will not modify packets received without tags 00=the switch will remove vlan tags from packets then add new tags to them. the inserted tag is the ingress port?s ?default tag?, which is indexed by port 0?s ?port based vlan index?. this is a replacement processi ng for tagged packets and an insertion for untagged packets 11 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 61 track id: jatr-1076-21 rev. 1.2 7.1.12. phy 0 register 24: port 0 control register 1 & vlan id [a] membership table 71. phy 0 register 24: port 0 contro l register 1 & vlan id [a] membership reg.bit name mode description default 24.[15:12 ] port 0 vlan index [3:0] rw in a port-based vlan configuration, this register indexes to port 0?s ?port vlan membership?, which can be defined in one of the registers ?vlan id [a] membership? to ?vlan id [p] membership?. port 0 can only communicate with members within this vlan. this register also indexes to a default port vid (pvid) for each port. the pvid is used in ta g insertion and f iltering if the tagged vid is not the same as the pvid. the default value of this register is 0000, which indexes to the vlan entry [a] that is composed of vlan id[a] membership bit [4:0] in phy0 reg.24.[4:0], and vlan id [a] in phy0 reg.25.[11:0]. 0000 24.11 internal use rw 1 24.10 internal use rw 1 24.9 internal use rw 1 24.8 internal use ro 0 24.7 internal use rw 1 24.6 internal use rw 1 24.5 reserved 0 24.[4:0] vlan id [a] membership bit [4:0] rw this 5-bit field specifies wh ich ports are the members of vlan a. if a destination addre ss look up fails, the packet associated with this vlan will be broadcast to the ports specified in this field. bit 0 stan ds for port 0, bit 4 stands for port 4.e.g.: 10001 means port 4 and 0 are the members of vlan a 10010 means port 4 and 1 are the members of vlan a 11111 means all 5 ports are the members of vlan a 1 0001 7.1.13. phy 0 register 25: port 0 control register 2 & vlan id [a] table 72. phy 0 register 25: port 0 register control 2 & vlan id [a] reg.bit name mode description default 25.15 internal use rw 1 25.14 internal use rw 1 25.13 internal use rw 1 25.12 internal use rw 1 25.[11:0] vlan id [a] rw defines the ieee 802.1q 12-bit vlan identifier of vlan a 0x000 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 62 track id: jatr-1076-21 rev. 1.2 7.1.14. phy 0 register 26: reserved or vlan id [f] membership 7.1.14.1 phy 0 register 26: reserved register (page=0) table 73. phy 0 register 26: reserved register reg.bit name mode description default 26.[15:0] reserved 0x5105 7.1.14.2 phy 0 register 26: vlan id [f] membership (page=1) table 74. phy 0 register 26: vlan id [f] membership reg.bit name mode description default 26.[15:5] reserved 1111 1111 111 26.[4:0] vlan id [f] membership bit [4:0] rw this 5-bit field specifies which ports are the members of vlan f. if a destination address look up fails, the packet associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan f 10010 means port 4 and 1 ar e the members of vlan f 11111 means all 5 ports are the members of vlan f 1 0001 7.1.15. phy 0 register 27: reserved or vlan id [f] 7.1.15.1 phy 0 register 27: reserved register (page=0) table 75. phy 0 register 27: reserved register reg.bit name mode description default 27.[15:0] reserved 0x0000 7.1.15.2 phy 0 register 27: vlan id [f] (page=1) table 76. phy 0 register 27: vlan id [f] reg.bit name mode description default 27.[15:12 ] reserved 1111 27.[11:0] vlan id [f] rw defines the ieee 802.1 q 12-bit vlan identifier of vlan f 0000 0000 0101 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 63 track id: jatr-1076-21 rev. 1.2 7.1.16. phy 0 register 28: reserved or vlan id [k] membership 7.1.16.1 phy 0 reg.28: reserved register (page=0) table 77. phy 0 register 28: reserved register reg.bit name mode description default 28.[15:0] reserved 0x0020 7.1.16.2 phy 0 register 28: vlan id [k] membership (page=1) table 78. phy 0 register 28: vlan id [k] membership reg.bit name mode description default 28.[15:5] reserved 1111 1111 111 28.[4:0] vlan id [k] membership bit [4:0] rw this 5-bit field specifies wh ich ports are the members of vlan k. if a destination address look up fails, the packet associated with this vlan will be broadcast to the ports specified in this field. bit 0 stan ds for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan k 10010 means port 4 and 1 ar e the members of vlan k 11111 means all 5 ports are the members of vlan k 1 0001 7.1.17. phy 0 register 29: reserved or vlan id [k] 7.1.17.1 phy 0 register 29: reserved register (page=0) table 79. phy 0 register 29: reserved register reg.bit name mode description default 29.[15:0] reserved 7.1.17.2 phy 0 register 29: vlan id [k] (page=1) table 80. phy 0 register 29: vlan id [k] reg.bit name mode description default 29.[15:12 ] reserved 1111 29.[11:0] vlan id [k] rw defines the ieee 802.1 q 12-bit vlan identifier of vlan k 0000 0000 1010 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 64 track id: jatr-1076-21 rev. 1.2 7.1.18. phy 0 register 30: reserved or vlan id [p] membership 7.1.18.1 phy 0 register 30: reserved register (page=0) table 81. phy 0 register 30: reserved register reg.bit name mode description default 30.[15:0] reserved 7.1.18.2 phy0 register 30: vlan id [p] membership (page=1) table 82. phy 0 register 30: vlan id [p] membership reg.bit name mode description default 30.[15:5] reserved 1111 1111 111 30.[4:0] vlan id [p] membership bit [4:0] rw this 5-bit field specifies wh ich ports are the members of vlan p. if a destination address look up fails, the packet associated with this vlan will be broadcast to the ports specified in this field. bit 0 stan ds for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan p 10010 means port 4 and 1 ar e the members of vlan p 11111 means all 5 ports are the members of vlan p 1 0001 7.1.19. phy 0 register 31: reserved or vlan id [p] 7.1.19.1 phy 0 register 31: reserved register (page=0) table 83. phy 0 register 31: reserved register reg.bit name mode description default 31.[15:0] reserved 7.1.19.2 phy 0 register 31: vlan id [p] (page=1) table 84. phy 0 register 31: vlan id [p] reg.bit name mode description default 31.[15:12 ] reserved 1111 31.[11:0] vlan id [p] rw defines the ieee 802.1 q 12-bit vlan identifier of vlan p 0000 0000 1111 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 65 track id: jatr-1076-21 rev. 1.2 7.2. phy 1 registers 7.2.1. phy 1 register 0 for port 1: control this register has the same de finition as phy 0 register 0 fo r port 0: control, page 53. 7.2.2. phy 1 register 1 for port 1: status this register has the same definition as p hy 0 register 1 for port 0: status, page 54. 7.2.3. phy 1 register 2 for port 1: phy identifier 1 this register has the same definition as phy 0 re gister 2 for port 0: p hy identifier 1, page 54. 7.2.4. phy 1 register 3 for port 1: phy identifier 2 this register has the same definition as phy 0 re gister 3 for port 0: p hy identifier 2, page 55. 7.2.5. phy 1 register 4 for port 1: auto-negotiation advertisement this register has the same definition as phy 0 regi ster 4 for port 0: auto-negotiation advertisement, page 55. 7.2.6. phy 1 register 5 for port 1: auto-negotiation link partner ability this register has the same definition as phy 0 regi ster 5 for port 0: auto -negotiation link partner ability, page 56. 7.2.7. phy 1 register 16~17: internal use register table 85. phy 1 register 16~17: internal use register reg.bit name mode description default 16 internal use rw 0xffff 17 internal use rw 0xffff 7.2.8. phy 1 register 18~19: internal use register table 86. phy 1 register 18~19: internal use register reg.bit name mode description default 18 internal use rw 0xffff 19 internal use rw 0xffff www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 66 track id: jatr-1076-21 rev. 1.2 7.2.9. phy 1 register 22: port 1 control register 0 this register has the same defi nition as phy 0 register 22: po rt 0 control register 0page 60. note: reg 22.8 is pin disportpri[1] strap opt ion for port 1. default value for 22.8 is 1. 7.2.10. phy 1 register 23: global option register 0 table 87. phy 1 register 23: global option register 0 reg.bit name mode description default 23.15 reserved 1 23.14 internal use rw 0 23.[13:8] reserved 00 1111 23.7 internal use rw 0 23.[6:5] reserved 10 23.4 internal use rw 1 23.[3:0] reserved 1111 7.2.11. phy 1 register 24: port 1 control register 1 & vlan id [b] membership table 88. phy 1 register 24: port 1 contro l register 1 & vlan id [b] membership reg.bit name mode description default 24.[15:12 ] port 1 vlan index [3:0] rw in a port-based vlan configuration, this register indexes to port 1?s ?port vlan membership?, which can be defined in one of the registers ?vlan id [a] membership? to ?vlan id [p] membership?. port 1can on ly communicate with members within this vlan. this register also indexes to a default port vid (pvid) for each port. the pvid is used in tag insertion and filtering if the tagged vid is not the same as the pvid. the default value of this register is 0001, which indexes to the vlan entry [b] that is composed of vlan id [b] membership bit [4:0] in phy1 reg.24.[4:0] and vlan id [b] in phy1 reg.25.[11:0]. 0001 24.11 internal use rw 1 24.10 internal use rw 1 24.9 internal use rw 1 24.8 internal use ro 0 24.7 internal use rw 1 24.6 internal use rw 1 24.5 reserved 0 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 67 track id: jatr-1076-21 rev. 1.2 reg.bit name mode description default 24.[4:0] vlan id [b] membership bit [4:0] rw this 5-bit field specifies which ports are the members of vlan b. if a destination address look up fails, the packet associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan b 10010 means port 4 and 1 ar e the members of vlan b 11111 means all 5 ports are members of vlan b 1 0010 7.2.12. phy 1 register 25: port 1 control register 2 & vlan id [b] table 89. phy 1 register 25: port 1 control register 2 & vlan entry [b] reg.bit name mode description default 25.15 internal use rw 1 25.14 internal use rw 1 25.13 internal use rw 1 25.12 internal use rw 1 25.[11:0] vlan id [b] rw defines the ieee 802.1 q 12-bit vlan identifier of vlan b 0000 0000 0001 7.2.13. phy 1 register 26: reserved or vlan id [g] membership 7.2.13.1 phy 1 register 26: reserved register (page=0) table 90. phy 1 register 26: reserved register reg.bit name mode description default 26.[15:0] reserved 0x031f 7.2.13.2 phy 1 register 26: vlan id [g] membership (page=1) table 91. phy 1 register 26: vlan id [g] membership reg.bit name mode description default 26.[15:5] reserved 1111 1111 111 26.[4:0] vlan id [g] membership bit [4:0] rw this 5-bit field specifies which po rts are the members of vlan g. if a destination address look up fa ils, the packet associated with this vlan will be broadcast to th e ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan g 10010 means port 4 and 1 ar e the members of vlan g 11111 means all 5 ports are members of vlan g 1 0010 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 68 track id: jatr-1076-21 rev. 1.2 7.2.14. phy 1 register 27: reserved or vlan id [g] 7.2.14.1 phy 1 register 27: reserved register (page=0) table 92. phy 1 register 27: reserved register reg.bit name mode description default 27.[15:0] reserved 0x1f10 7.2.14.2 phy 1 register 27: vlan id [g] (page=1) table 93. phy 1 register 27: vlan id [g] reg.bit name mode description default 27.[15:12 ] reserved 1111 27.[11:0] vlan id [g] rw defines the ieee 802.1 q 12-bit vlan identifier of vlan g 0000 0000 0110 7.2.15. phy 1 register 28: reserved or vlan id [l] membership 7.2.15.1 phy 1 register 28: reserved register (page=0) table 94. phy 1 register 28: reserved register reg.bit name mode description default 28.[15:0] reserved 0x0012 7.2.15.2 phy 1 register 28: vlan id [l] membership (page=1) table 95. phy 1 register 28: vlan id [l] membership reg.bit name mode description default 28.[15:5] reserved 1111 1111 111 28.[4:0] vlan id [l] membership bit [4:0] rw this 5-bit field specifies wh ich ports are the members of vlan l. if a destination address look up fails, the packet associated with this vlan will be broadcast to the ports specified in this field. bit 0 stan ds for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan l 10010 means port 4 and 1 ar e the members of vlan l 11111 means all 5 ports are members of vlan l 1 0010 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 69 track id: jatr-1076-21 rev. 1.2 7.2.16. phy 1 register 29: reserved or vlan id [l] 7.2.16.1 phy 1 register 29: reserved (page=0) table 96. phy 1 register 29: reserved register reg.bit name mode description default 29.[15:0] reserved 0x02c5 7.2.16.2 phy 1 register 29: vlan id [l] (page=1) table 97. phy 1 register 29: vlan id [l] reg.bit name mode description default 29.[15:12 ] reserved 1111 29.[11:0] vlan id [l] rw defines the ie ee 802.1q 12-bit vlan identifier of vlan l 0000 0000 1011 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 70 track id: jatr-1076-21 rev. 1.2 7.3. phy 2 registers 7.3.1. phy 2 register 0 for port 2: control this register has the same de finition as phy 0 register 0 fo r port 0: control, page 53. 7.3.2. phy 2 register 1 for port 2: status this register has the same definition as p hy 0 register 1 for port 0: status, page 54. 7.3.3. phy 2 register 2 for port 2: phy identifier 1 this register has the same definition as phy 0 re gister 2 for port 0: p hy identifier 1, page 54. 7.3.4. phy 2 register 3 for port 2: phy identifier 2 this register has the same definition as phy 0 re gister 3 for port 0: p hy identifier 2, page 55. 7.3.5. phy 2 register 4 for port 2: auto-negotiation advertisement this register has the same definition as phy 0 regi ster 4 for port 0: auto-negotiation advertisement, page 55. 7.3.6. phy 2 register 5 for port 2: auto-negotiation link partner ability this register has the same definition as phy 0 regi ster 5 for port 0: auto -negotiation link partner ability, page 56. 7.3.7. phy 2 register 16~17: internal use register table 98. phy 2 register 16~17: internal use register reg.bit name mode description default 16 internal use rw 0xffff 17 internal use rw 0xffff 7.3.8. phy 2 register 18~19: internal use register table 99. phy 2 register 18~19: internal use register reg.bit name mode description default 18 internal use rw 0xffff 19 internal use rw 0xffff www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 71 track id: jatr-1076-21 rev. 1.2 7.3.9. phy 2 register 22: port 2 control register 0 this register has the same definition as phy 0 re gister 22: port 0 control register 0, on page 60. note: reg 22.8 is pin disportpri[2] strap opt ion for port 2. default value for 22.8 is 1. 7.3.10. phy 2 register 23: global option 1 register table 100. phy 2 register 23: global option register 1 reg.bit name mode description default 23.[15:12 ] reserved 0000 23.11 internal use rw 0 23.10 internal use rw 0 23.9 internal use rw 0 23.[8:0] reserved 0 0010 0000 7.3.11. phy 2 register 24: port 2 control register 2 & vlan id [c] membership table 101. phy 2 register 24: port 2 control register 2 & vlan id [c] membership reg.bit name mode description default 24.[15:12 ] port 2 vlan index [3:0] rw in a port-based vlan configuration, this register indexes to port 2?s ?port vlan membership?, which can be defined in one of the registers ?vlan id [a] membership? to ?vlan id [p] membership?. port 2 can on ly communicate with members within this vlan. this register also indexes to a default port vid (pvid) for each port. the pvid is used in tag insertion and filtering if the tagged vid is not the same as the pvid. the default value of this register is 0010, which indexes to the vlan entry [c] that is composed of vlan id [c] membership bit [4:0] in phy2 reg.24.[4:0], and vlan id [c] in phy2 reg.25.[11:0]. 0010 24.11 internal use rw 1 24.10 internal use rw 1 24.9 internal use rw 1 24.8 internal use ro 0 24.7 internal use rw 1 24.6 internal use rw 1 24.5 reserved 0 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 72 track id: jatr-1076-21 rev. 1.2 reg.bit name mode description default 24.[8:0] vlan id [c] membership bit [4:0] rw this 5-bit field specifies which ports are the members of vlan c. if a destination address look up fails, the packet associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan c 10010 means port 4 and 1 ar e the members of vlan c 11111 means all 5 ports are the members of vlan c 1 0100 7.3.12. phy 2 register 25: port 2 control register 3 & vlan id [c] table 102. phy 2 register 25: port 2 control register 3 & vlan id [c] reg.bit name mode description default 25.15 internal use rw 1 25.14 internal use rw 1 25.13 internal use rw 1 25.12 internal use rw 1 25.[11:0] vlan id [c] rw defines the ie ee 802.1q 12-bit vlan identifier of vlan c 0000 0000 0010 7.3.13. phy 2 register 26: reserved or vlan id [h] membership 7.3.13.1 phy 2 register 26: reserved register (page=0) table 103. phy 2 register 26: reserved register reg.bit name mode description default 26.[15:0] reserved 0x0052 7.3.13.2 phy 2 register 26: vlan id [h] membership (page=1) table 104. phy 2 register 26: vlan id [h] membership reg.bit name mode description default 26.[15:5] reserved 1111 1111 111 26.[4:0] vlan id [h] membership bit [4:0] rw this 5-bit field specifies which ports are the members of vlan h. if a destination address look up fails, the packet associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan h 10010 means port 4 and 1 ar e the members of vlan h 11111 means all 5 ports are the members of vlan h 1 0100 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 73 track id: jatr-1076-21 rev. 1.2 7.3.14. phy 2 register 27: reserved or vlan id [h] 7.3.14.1 phy 2 register 27: reserved register (page=0) table 105. phy 2 register 27: reserved register reg.bit name mode description default 27.[15:0] reserved 0xa9cd 7.3.14.2 phy 2 register 27: vlan id [h] (page=1) table 106. phy 2 register 27: vlan id [h] reg.bit name mode description default 27.[15:12 ] reserved 1111 27.[11:0] vlan id [h] rw defines the ie ee 802.1q 12-bit vlan identifier of vlan h 0000 0000 0111 7.3.15. phy 2 register 28: reserved or vlan id [m] membership 7.3.15.1 phy 2 register 28: reserved register (page=0) table 107. phy 2 register 28: reserved register reg.bit name mode description default 28.[15:0] resreved 0xb029 7.3.15.2 phy 2 register 28: vlan id [m] membership (page=1) table 108. phy 2 register 28: vlan id [m] membership reg.bit name mode description default 28.[15:5] reserved 1111 1111 111 28.[4:0] vlan id [m] membership bit [4:0] rw this 5-bit field specifies which ports are the members of vlan m. if a destination address look up fails, the packet associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan m 10010 means port 4 and 1 ar e the members of vlan m 11111 means all 5 ports are the members of vlan m 1 0100 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 74 track id: jatr-1076-21 rev. 1.2 7.3.16. phy 2 register 29: reserved or vlan id [m] 7.3.16.1 phy 2 register 29: reserved register (page=0) table 109. phy 2 register 29: reserved register reg.bit name mode description default 29.[15:0] reserved 0xb01f 7.3.16.2 phy 2 register 29: vlan id [m] (page=1) table 110. phy 2 register 29: vlan id [m] reg.bit name mode description default 29.[15:12 ] reserved 1111 29.[11:0] vlan id [m] rw defines the ie ee 802.1q 12-bit vlan identifier of vlan m. 0000 0000 1100 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 75 track id: jatr-1076-21 rev. 1.2 7.4. phy 3 registers 7.4.1. phy 3 register 0 for port 3: control this register has the same de finition as phy 0 register 0 fo r port 0: control, page 53. 7.4.2. phy 3 register 1 for port 3: status this register has the same definition as p hy 0 register 1 for port 0: status, page 54. 7.4.3. phy 3 register 2 for port 3: phy identifier 1 this register has the same definition as phy 0 re gister 2 for port 0: p hy identifier 1, page 54. 7.4.4. phy 3 register 3 for port 3: phy identifier 2 this register has the same definition as phy 0 re gister 3 for port 0: p hy identifier 2, page 55. 7.4.5. phy 3 register 4 for port 3: auto-negotiation advertisement this register has the same definition as phy 0 regi ster 4 for port 0: auto-negotiation advertisement, page 55. 7.4.6. phy 3 register 5 for port 3: auto-negotiation link partner ability this register has the same definition as phy 0 regi ster 5 for port 0: auto -negotiation link partner ability, page 56. 7.4.7. phy 3 register 16~18: switch mac address the switch mac address is used as the sour ce address in mac pause control frames. table 111. phy 3 register 16~18: switch mac address reg.bit name mode description default 16 switch mac address [47:32] rw 16.[15:8] = switch mac address byte 4 16.[7:0] = switch mac address byte 5 0x5452 17 switch mac address [31:16] rw 17.[15:8] = switch mac address byte 2 17.[7:0] = switch mac address byte 3 0x834c 18 switch mac address [15:0] rw 18.[15:8] = switch mac address byte 0 18.[7:0] = switch mac address byte 1 0xc005 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 76 track id: jatr-1076-21 rev. 1.2 7.4.8. phy 3 register 19~21: internal use register table 112. phy 3 register 19~21: internal use register reg.bit name mode description default 19 internal use rw 0x0000 20 internal use rw 0x0000 21 internal use rw 0x0000 7.4.9. phy 3 register 22: port 3 control register 0 this register has the same definition as phy 0 re gister 22: port 0 control register 0, on page 60. note: reg 22.8 is pin disportpri[3] strap opt ion for port 3. default value for 22.8 is 1. 7.4.10. phy 3 register 24: port 3 control register 1 & vlan id [d] membership table 113. phy 3 register 24: port 3 control register 1 & vlan id [d] membership reg.bit name mode description default 24.[15:12 ] port 3 vlan index [3:0] rw in a port-based vlan configuration, this register indexes to port 3?s ?port vlan membership?, which can be defined in one of the registers ?vlan id [a] membership? to ?vlan id [p] membership?. port 3 can on ly communicate with members within this vlan. this register also indexes to a default port vid (pvid) for each port. the pvid is used in tag insertion and filtering if the tagged vid is not the same as the pvid. the default value of this register is 0011, which indexes to the vlan entry [d] that is composed of vlan id [d] membership bit [4:0] in phy3 reg.24.[4:0], and vlan id [d] in phy3 reg.25.[11:0]. 0011 24.11 internal use rw 1 24.10 internal use rw 1 24.9 internal use rw 1 24.8 internal use ro 0 24.7 internal use rw from pin default=1 24.6 internal use rw 1 24.5 reserved 0 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 77 track id: jatr-1076-21 rev. 1.2 reg.bit name mode description default 24.[4:0] vlan id [d] membership bit [4:0] rw this 5-bit field specifies which ports are the members of vlan d. if a destination address look up fails, the packet associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan d 10010 means port 4 and 1 ar e the members of vlan d 11111 means all 5 ports are the members of vlan d 1 1000 7.4.11. phy 3 register 25: port 3 control register 2 & vlan id [d] table 114. phy 3 register 25: port 3 control register 2 & vlan id [d] reg.bit name mode description default 25.15 internal use rw 1 25.14 internal use rw 1 25.13 internal use rw 1 25.12 internal use rw 1 25[11:0] vlan id [d] rw defines the ie ee 802.1q 12-bit vlan identifier of vlan d 0000 0000 0011 7.4.12. phy 3 register 26: reserved or vlan id [i] membership 7.4.12.1 phy 3 register 26: reserved register (page=0) table 115. phy 3 register 26: reserved register reg.bit name mode description default 26.[15:0] reserved 0x9668 7.4.12.2 phy 3 register 26: vlan id [i] membership (page=1) table 116. phy 3 register 26: vlan id [i] membership reg.bit name mode description default 26.[15:5] reserved 1111 1111 111 26.[4:0] vlan id [i] membership bit [4:0] rw this 5-bit field specifies which ports are the members of vlan i. if a destination address look up fails, the packet associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan i 10010 means port 4 and 1 ar e the members of vlan i 11111 means all 5 ports are the members of vlan i 1 1000 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 78 track id: jatr-1076-21 rev. 1.2 7.4.13. phy 3 register 27: reserved or vlan id [i] 7.4.13.1 phy 3 register 27: reserved register (page=0) table 117. phy 3 register 27: reserved register reg.bit name mode description default 27.[15:0] reserved 0xa464 7.4.13.2 phy 3 register 27: vlan id [i] (page=1) table 118. phy 3 register 27: vlan id [i] reg.bit name mode description default 27.[15:12 ] reserved 1111 27.[11:0] vlan id [i] rw defines the ie ee 802.1q 12-bit vlan identifier of vlan i 0000 0000 1000 7.4.14. phy 3 register 28: reserved or vlan id [n] membership 7.4.14.1 phy 3 register 28: reserved register (page=0) table 119. phy 3 register 28: reserved register reg.bit name mode description default 28.[15:0] reserved 0x9458 7.4.14.2 phy 3 register 28: vlan id [n] membership (page=1) table 120. phy 3 register 28: vlan id [n] membership reg.bit name mode description default 28.[15:5] reserved 1111 1111 111 28.[4:0] vlan id [n] membership bit [4:0] rw this 5-bit field specifies wh ich ports are the members of vlan n. if a destination address look up fails, the packet associated with this vlan will be broadcast to the ports specified in this field. bit 0 stan ds for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan n 10010 means port 4 and 1 ar e the members of vlan n 11111 means all 5 ports are the members of vlan n 1 1000 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 79 track id: jatr-1076-21 rev. 1.2 7.4.15. phy 3 register 29: reserved or vlan id [n] 7.4.15.1 phy 3 register 29: reserved register (page=0) table 121. phy 3 register 29: reserved register reg.bit name mode description default 29.[15:0] reserved 0x2154 7.4.15.2 phy 3 register 29: vlan id [n] (page=1) table 122. phy 3 register 29: vlan id [n] reg.bit name mode description default 29.[15:12 ] reserved 1111 29.[11:0] vlan id [n] rw defines the ie ee 802.1q 12-bit vlan identifier of vlan n. 0000 0000 1101 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 80 track id: jatr-1076-21 rev. 1.2 7.5. phy 4 registers 7.5.1. phy 4 register 0 for port 4: control this register has the same de finition as phy 0 register 0 fo r port 0: control, page 53. 7.5.2. phy 4 register 1 for port 4: status this register has the same definition as p hy 0 register 1 for port 0: status, page 54. 7.5.3. phy 4 register 2 for port 4: phy identifier 1 this register has the same definition as phy 0 re gister 2 for port 0: p hy identifier 1, page 54. 7.5.4. phy 4 register 3 for port 4: phy identifier 2 this register has the same definition as phy 0 re gister 3 for port 0: p hy identifier 2, page 55. 7.5.5. phy 4 register 4 for port 4: auto-negotiation advertisement this register has the same definition as phy 0 regi ster 4 for port 0: auto-negotiation advertisement, page 55. 7.5.6. phy 4 register 5 for port 4: auto-negotiation link partner ability this register has the same definition as phy 0 regi ster 5 for port 0: auto -negotiation link partner ability, page 56. 7.5.7. phy 4 register 16: indirect access control phy 4 register 16 is used for reading or writing data to the mac address table. table 123. phy 4 register 16: indirect access control reg.bit name mode description default 16.[15:2] reserved 0000 0000 0000 00 16.1 command execution rw 1: trigger a command to read or write lookup table 0: indicate this command is done 0 16.0 read or write operation rw 1: read cycle 0: write cycle 0 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 81 track id: jatr-1076-21 rev. 1.2 7.5.8. phy 4 register 17~20: indirect access data table 124. phy 4 register 17~20: indirect access data reg.bit name mode description default 17 indirect data 0 [15:0] rw indirect data 0 [6] = if this bit is 1, indicates this entry is static and will never be aged out. if this bit is 0, indicates this entry is dynamically learned, aged, updated, and deleted. indirect data [5:4] = 2-bit counter for internal aging. (10->11->01->00) indirect data [3:0] = the sour ce port of this source mac address id learned indirect data 0 [15:7] = reserved. 0x00 18 indirect data 1 [15:0] rw indirect data 1 [15:8] = source mac address [7:0] (byte 5) indirect data 1 [7:0] = source mac address [15:8] (byte 4) indirect data 1 [1:0] and indirect data 1 [15:8] of this register also determine the entry index [9:0] in the lookup table of this accessed data. indirect data 1 [1:0] = entry index [9:8] indirect data 1 [15:8] = entry index [7:0] in the write cycle: entry index [9:0] indirectly maps to an entry in the lookup table for writing. the written data must be the source mac address [47:10] and entry index [9:0]. in the read cycle: entry index [9:0] indirectly maps to an entry in the lookup table for reading. the read back data will be shown in indirect data 0, 1, 2, and 3. 0x00 19 indirect data 2 [15:0] rw indirect data 2 [7:0] = source mac address [31:24] (byte 3) indirect data 2 [15:8] = source mac address [23:16] (byte 2) 0x00 20 indirect data 3 [15:0] rw indirect data 3 [7:0] = source mac address [47:40] (byte 1) indirect data 3 [15:8] = source mac address [39:32] (byte 0) 0x00 7.5.9. phy 4 register 21: 802.1p base priority table 125. phy 2 register 20: 802.1p base priority reg.bit name mode description default 21.[15.13 ] 802.1p base priority rw classifies priority for inco ming ieee 802.1q packets, if ieee 802.1p prior ity classification is enabled. ?user priority? is compared against this value. >=: classify as high priority <: classify as low priority 100 21.[12:7] reserved 0 0000 0 21.[6:4] internal use rw 100 21.3 reserved 0 21.[2:0] internal use rw 000 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 82 track id: jatr-1076-21 rev. 1.2 7.5.10. phy 4 register 22: port 4 control register 0 this register has the same definition as phy 0 re gister 22: port 0 control register 0, on page 60. note: reg 22.8 is not pin disportpri[4] strap option for port 4. default value for 22.8 is 1. 7.5.11. phy 4 register 24: port 4 control register 1 & vlan id [e] membership table 126. phy 4 register 24: port 4 control register 1 & vlan id [e] membership reg.bit name mode description default 24.[15:12 ] port 4 vlan index [3:0] rw in a port-based vlan configuration, this register indexes to port 4?s ?port vlan membership?, which can be defined in one of the registers ?vlan id [a] membership? to ?vlan id [p] membership?. port 4 can on ly communicate with members within this vlan. this register also indexes to a default port vid (pvid) for each port. the pvid is used in tag insertion and filtering if the tagged vid is not the same as the pvid. the default value of this register is 0100, which indexes to the vlan entry [e] that is composed of vlan id [e] membership bit [4:0] in phy4 reg.24.[4:0] , and vlan id [e] in phy4 reg.25.[11:0]. 0100 24.11 internal use rw 1 24.10 internal use rw 1 24.9 internal use rw 1 24.8 internal use ro 0 24.7 internal use rw 1 24.6 internal use rw 1 24.5 reserved 0 24.[4:0] vlan id [e] membership bit [4:0] rw this 5-bit field specifies which ports are the members of vlan e. if a destination address look up fails, the packet associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan e 10010 means port 4 and 1 ar e the members of vlan e 11111 means all 5 ports are the members of vlan e 1 1111 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 83 track id: jatr-1076-21 rev. 1.2 7.5.12. phy 4 register 25: port 4 control register 2 & vlan id [e] table 127. phy 4 register 25: port 4 control register 2 & vlan id [e] reg.bit name mode description default 25.15 internal use rw 1 25.14 internal use rw 1 25.13 internal use rw 1 25.12 internal use rw 1 25.[11:0] vlan id [e] rw defines the ie ee 802.1q 12-bit vlan identifier of vlan e 0000 0000 0100 7.5.13. phy 4 register 26: reserved or vlan id [j] membership 7.5.13.1 phy 4 register 26: reserved register (page=0) table 128. phy 4 register 26: reserved register reg.bit name mode description default 26.[15:0] reserved 0x07d0 7.5.13.2 phy 4 register 26: vlan id [j] membership (page=1) table 129. phy 4 register 26: vlan id [j] membership reg.bit name mode description default 26.[15:5] reserved 1111 1111 111 26.[4:0] vlan id [j] membership bit [4:0] rw this 5-bit field specifies which ports are the members of vlan j. if a destination address look up fails, the packet associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan j 10010 means port 4 and 1 ar e the members of vlan j 11111 means all 5 ports are the members of vlan j 1 1111 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 84 track id: jatr-1076-21 rev. 1.2 7.5.14. phy 4 register 27: reserved or vlan id [j] 7.5.14.1 phy 4 register 27: reserved register (page=0) table 130. phy 4 register 27: reserved register reg.bit name mode description default 27.[15:0] reserved 7.5.14.2 phy 4 register 27: vlan id [j] (page=1) table 131. phy 4 register 27: vlan id [j] reg.bit name mode description default 27.[15:12 ] reserved 1111 27.[11:0] vlan id [j] rw defines the ie ee 802.1q 12-bit vlan identifier of vlan j 0000 0000 1001 7.5.15. phy 4 register 28: reserved or vlan id [o] membership 7.5.15.1 phy 4 register 28: reserved register (page=0) table 132. phy 4 register 28: reserved register reg.bit name mode description default 28.[15:0] reserved 7.5.15.2 phy 4 register 28: vlan id [o] membership (page=1) table 133. phy 4 register 28: vlan id [o] membership reg.bit name mode description default 28.[15:5] reserved 1111 1111 111 28.[4:0] vlan id [o] membership bit [4:0] rw this 5-bit field specifies which ports are the members of vlan o. if a destination address look up fails, the packet associated with this vlan will be broadcast to the ports specified in this field. bit 0 stands for port 0, bit 4 stands for port 4. e.g.: 10001 means port 4 and 0 ar e the members of vlan o 10010 means port 4 and 1 ar e the members of vlan o 11111 means all 5 ports are the members of vlan o 1 1111 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 85 track id: jatr-1076-21 rev. 1.2 7.5.16. phy 4 register 29: reserved or vlan id [o] 7.5.16.1 phy 4 register 29: reserved register (page=0) table 134. phy 4 register 29: reserved register reg.bit name mode description default 29.[15:0] reserved 7.5.16.2 phy 4 register 29: vlan id [o] (page=1) table 135. phy 4 register 29: vlan id [o] reg.bit name mode description default 29.[15:12 ] reserved 1111 29.[11:0] vlan id [o] rw defines the ie ee 802.1q 12-bit vlan identifier of vlan o 0000 0000 1110 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 86 track id: jatr-1076-21 rev. 1.2 7.6. phy 5 registers 7.6.1. phy 5 register 0 for port 4 mac: control note: this register only works in mii phy and sni phy mode. in mii mac mode, these registers have no meaning. table 136. phy 5 register 0: control reg.bit name mode description default 0.15 reset ro 0: no reset allowed (permanently=0) 0 0.14 loopback (digital loopback) ro 0: normal operation (permanently=0) 0 0.13 speed select rw 1: 100mbps 0: 10mbps when nway is enabled, this bit reflects the result of auto- negotiation (read only). when nway is disabled, this bit can be set through smi (read/write). pin p4spdsta strap option 0.12 auto negotiation enable rw 1: enable auto-negotiation process 0: disable auto-negotiation process this bit can be set through smi (read/write). pin p4aneg strap option 0.11 power down ro 0: normal operation (permanently=0) 0 0.10 isolate ro 0: normal operation (permanently=0) 0 0.9 restart auto negotiation ro 0: normal operation (permanently=0) 0 0.8 duplex mode rw 1: full duplex operation 0: half duplex operation when nway is enabled, this bit reflects the result of auto- negotiation (read only). when nway is disabled, this bit may be set through smi (read/write). pin p4dupsta strap option 0.[7:0] reserved 0000 0000 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 87 track id: jatr-1076-21 rev. 1.2 7.6.2. phy 5 register 1 for port 4 mac: status note: this register only works in mii phy and sni phy mode. in mii mac mode, these registers have no meaning. table 137. phy 5 register 1: status reg.bit name mode description default 1.15 100base_t4 ro 0: no 100base-t4 capability 0 1.14 100base_tx_fd ro 1: 100base-tx full duplex capable (permanently=1) 1 1.13 100base_tx_hd ro 1: 100base-tx half duplex capable (permanently=1) 1 1.12 10base_t_fd ro 1: 10base-tx full duplex capable (permanently=1) 1 1.11 10base_t_hd ro 1: 10base-tx half duplex capable (permanently=1) 1 1.[10:7] reserved ro 0 1.6 mf preamble suppression ro the RTL8305SC will accept manageme nt frames with preamble suppressed (permanently=1) 1 1.5 auto-negotiate complete ro 1: auto-negotiation process completed. mii reg.4, 5 are valid if this bit is set (permanently=1) 1 1.4 remote fault ro 0: no remote fault (permanently=0) 0 1.3 auto-negotiation ability ro 1: nway auto-negotiation capable (permanently=1) 1 1.2 link status ro 1: link is established 0: link is failed this bit reflects the status of pin p4lnksta# in real time. pin p4lnksta# strap option 1.1 jabber detect ro 0: no ja bber detected (permanently=0) 0 1.0 extended capability ro 1: extended register capable (permanently=1) 1 7.6.3. phy 5 register 2 for po rt 4 mac: phy identifier 1 table 138. phy 5 register 2: phy identifier 1 reg.bit name mode description default 2.[15:0] oui ro composed of the 3 rd to 18 th bits of the organizationally unique identifier (oui), respectively 0x001c 7.6.4. phy 5 register 3 for po rt 4 mac: phy identifier 2 table 139. phy 5 register 3: phy identifier 2 reg.bit name mode description default 3.[15:10] oui ro assigned to the 19 th through 24 th bits of the oui 1100 10 3.[9:4] model number ro manufacturer?s model number (05: indicates rtl8305 00 0101 3.[3:0] revision number ro manufacturer?s revision number (02: indicates sc 0010 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 88 track id: jatr-1076-21 rev. 1.2 7.6.5. phy 5 register 4 for port 4 mac: auto-negotiation advertisement note: this register only works in phy mode mii and phy mode sni. in mac mode mii, these registers have no meaning. table 140. phy 5 register 4: auto-negotiation advertisement reg.bit name mode description default 4.15 next page ro 1: next page enabled 0: next page disabled (permanently=0) 0 4.14 acknowledge ro permanently=0. 0 4.13 remote fault ro 1: advertises that the RTL8305SC has detected a remote fault 0: no remote fault detected 0 4.[12:11] reserved ro 0 4.10 pause rw 1: advertises that the RTL8305SC possesses 802.3x flow control capability 0: no flow control capability pin p4flctrl strap option 4.9 100base-t4 ro technology not supported (permanently=0) 0 4.8 100base-tx-fd rw 1: 100base-tx full duplex capable 0: not 100base-tx full duplex capable pin p4dupsta and p4spdsta strap option 4.7 100base-tx rw 1: 100base-tx half duplex capable 0: not 100base-tx half duplex capable pin p4spdsta strap option 4.6 10base-t-fd rw 1: 10base-tx full duplex capable 0: not 10base-tx full duplex capable pin p4dupsta or p4spdsta strap option 4.5 10base-t rw 1: 10base-tx half duplex capable 0: not 10base-tx half duplex capable 1 4.[4:0] selector field ro [00001]=ieee 802.3 0 0001 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 89 track id: jatr-1076-21 rev. 1.2 7.6.6. mii port nway mode table 141. mii port nway mode event description upon reset strapping p4spdsta=1 and p4dupsta=1 reg0.13=1, reg0.8=1 strapping p4spdsta=1 and p4dupsta=0 reg0.13=1, reg0.8=0 strapping p4spdsta=0 and p4dupsta=1 reg0.13=0, reg0.8=1 strapping p4spdsta=0 and p4dupsta=0 reg0.13=0, reg0.8=0 defau1t value of reg4.10 is strapped from pin p4flctrl default value of reg1.2 is strapped from pin p4lnksta# p4lnksta# pulled down reg1.2=1 p4lnksta# pulled up reg1.2=0 after reset if phy 5 register 4 is configured as reg4.8=1, reg4.7=1, reg4.6=1, reg4.5=1, the RTL8305SC will reflect this configuration in phy 8 register 0 as reg0.13=1 and reg0.8=1 if phy 5 register 4 is configured as reg4.8=0, reg4.7=1, reg4.6=1, reg4.5=1, the RTL8305SC will reflect this configuration in phy 8 register 0 as reg0.13=1 and reg0.8=0 if phy 5 register 4 is configured as reg4.8=0, reg4.7=0, reg4.6=1, reg4.5=1, the RTL8305SC will reflect this configuration in phy 8 register 0 as reg0.13=0 and reg0.8=1 if phy 5 register 4 is configured as reg4.8=0, reg4.7=0, reg4.6=0, reg4.5=1, the RTL8305SC will reflect this configuration in phy 8 register 0 as reg0.13=0 and reg0.8=0 if the cpu polls register 5, the RTL8305SC replies with the contents in register 4 if the cpu polls register 4, the RTL8305SC replies with the contents in register 4 7.6.7. mii port force mode table 142. mii port force mode event description upon reset strapping p4spdsta=1 and p4dupsta=1 reg0.13=1, reg0.8=1 strapping p4spdsta=1 and p4dupsta=0 reg0.13=1, reg0.8=0 strapping p4spdsta=0 and p4dupsta=1 reg0.13=0, reg0.8=1 strapping p4spdsta=0 and p4dupsta=0 reg0.13=0, reg0.8=0 defau1t value of reg4.10 is strapped from pin p4flctrl default value of reg1.2 is strapped from pin p4lnksta# p4lnksta# pulled down reg1.2=1 p4lnksta# pulled up reg1.2=0 after reset the cpu only writes register 0.13 and 0.8 to propose a link configuration, then reads register 1.2 to determine whether the link partner can accept this link configuration www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 90 track id: jatr-1076-21 rev. 1.2 8. functional description 8.1. switch core functional overview 8.1.1. applications the RTL8305SC is a 5-port fast ethernet switch contro ller that integrates memo ry, five macs, and five physical layer transceivers for 10b ase-t and 100base-tx operation into a single chip. all ports support 100base-fx, which shares pins (tx+-/rx+-) with utp ports and needs no sd+/- pins, a development using realtek proprietary technology. to compensate for the lack of auto-n egotiation in 100base-fx applications, the RTL8305SC can be fo rced into 100base-fx ha lf or full duplex mode, and can enable or disable flow control in fiber mode. the five ports are separated into three groups (groupx/g roupy/port4) for flexible port configuration using strapping pins upon reset. the setgroup pin is used to select the port numbers for groupx and groupy (setgroup=1: groupx = port 0; groupy = ports 1, 2, and 3. setgroup=0: groupx = ports 0 and 1; groupy = ports 2 and 3). th e gxmode/gymode/p4mode[1:0] pins ar e used to select the operation mode (utp/fx for groupx and groupy, utp/fx/phy mode mii/p hy mode sni/mac mode mii for port 4). upon reset, in addition to using strapping pins, the rtl 8305sc can be configured with an eeprom or read/write ope ration by a cpu via the mdc/mdio interface. for more detailed system application circu its, refer to applicati on information, page 141. note: upon reset: defined as a short time after the end of a hardware reset. after reset: defined as the time af ter the specified ?upon reset? time. 8.1.2. port 4 operating mode of port 4 each port has two parts: mac and phy. in utp and fx mode, port 4 uses both the mac and internal phy parts like the other ports. in other modes, port 4 uses only the mac part, which provides an external interface to connect to the extern al mac or phy. two pins are used for these operation mode configurations: p4mode[1:0]. port 4 supports an external mac interface which can be set to phy mode mii, phy mode sni, or mac mode mii to work with the external mac of a r outing engine, phy of a ho mepna, or other physical layer transceiver. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 91 track id: jatr-1076-21 rev. 1.2 if the mac part of port 4 connects w ith an external mac, such as the pr ocessor of a router application, it will act as a phy. this is phy mode mii, or p hy mode sni. in phy mode mii or phy mode sni, port 4 uses the mac part only, and provides an exte rnal mac interface to connect macs of external devices. in order to connect both ma cs, the mii of the switch mac should be reversed into phy mode. if the mac part of port 4 connects with an external phy, such as the phy of a homepna application, port 4 will act as a mac. this is mac mode mii. in mac mode mii, port 4 us es its mac to connect to an external phy and ignores the internal phy part. external mac interface in order to act as a phy when port 4 is in phy m ode, some pins of the exte rnal mac interface must be changed. for example, txc are input pins for mac, but output pins for phy. the mtxc/prxc pin is input for mac mode and output for phy mode. refer to figure 3, pa ge 93 to check the relationship between the RTL8305SC and the external device. tip: connect the input of the RTL8305SC to the output of the external device. the RTL8305SC has no rxer, txer, and crs pins for mii signaling. b ecause the RTL8305SC does not support pin crs, it is necessary to connect the mtxen/pr xdv (output) of phy mode to both crs and rxdv (input) of the external device. port 4 status pins when p4mode[1:0]=11, port 4 can be either utp or mac mode mii. port 4 will automatically detect the link status of utp from the internal phy, and the link status of mac mode mii from both the txc of the external phy and from p4lnksta#. if bot h utp and mii port are linked ok, utp has higher priority and the RTL8305SC will igno re the signal of the mii port. in utp and fx mode, the internal phy will provi de the port status (link/speed/duplex/full flow control ability) in real time. in order to provide th e initial configuration of port 4?s phy (utp or fx mode), four pins (p4aneg, p4full, p4spd100, p4enfc) are used to strap upon reset. however, three of these pins are also used for port 4?s mac (the ot her three modes) in real time after reset (p4spd100 -> p4spdsta, p4full -> p4dupsta, p4enfc -> p4flctrl). in the other three modes, four pins (p4lnksta#, p4spdsta, p4dupsta, p4flctrl) are necessary in order to provide the port status to port 4?s mac. that means that the external mac or phy should be forced to the same port status as port 4?s mac. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 92 track id: jatr-1076-21 rev. 1.2 related pins when port 4 is in utp or fx mode, the leds of port 4 are used to display phy status. when port 4 is in other modes, the leds of port 4 ar e used to display mac status. four parallel leds corresponding to port 4 can be tri-stated (disable led functions) for mii port application by setting enp4led in eeprom to 0. in utp applications, this bit should be 1. the sel_miimac# pin can be used to indicate m ii mac port active after reset for the purposes of utp/mii auto-detection. one 25mhz clock output (pin ck25mout) can be used as a clock source for the underlying homepna/other phy physical devices. phy mode mii/phy mode sni in routing applications, the rtl 8305sc cooperates with a routing engi ne to communicate with the wan (wide area network) through mii/sni. in such applications, p4lnks ta# =0 and p4mode[1] is pulled low upon reset. p4mode[0] determines whet her mii or sni mode is selected. in mii (nibble) mode (p4mode[0]=1), p4spdsta=1 re sults in mii operating at 100mbps with mtxc, and mrxc runs at 25mhz; however, p4spdsta=0 l eads to mii operating at 10mbps with mtxc, and mrxc runs at 2.5mhz. in sni (serial) mode (p4mode[0]=0), p4spdsta ha s no effect and should be pulled-down. sni mode operates at 10mbps only, with mtxc and mrxc running at 10mhz. in sni mode the RTL8305SC does not loopback an rxdv signal as a response to tx en, and does not support the heartbeat function (asserting col signal for each complete txen signal). www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 93 track id: jatr-1076-21 rev. 1.2 59-mrxc/ptxc 60-mrxdv/ptxen 67~61-mrxd[3:0]/ptxd[3:0] 51-mtxc/prxc 52-mtxen/prxdv 57~54-mtxd[3:0]/prxd[3:0] 58-mcol/pcol rxc crs rxdv rxd[3:0] txc txen txd col 4 4 vdsl/ homepna/ single phy 44-p4mode[1] 45-p4mode[0] 49-p4lnksta# 47-p4spdsta/p4full 48-p4dupst a/p4spd100 46-p4flctrl/p4enfc floating=high floating=high note 1 note 2 note 3 68-selmiimac#/disdspri led indication mac mode mii pull down=link on 59-mrxc/ptxc 60-mrxdv/ptxen 67~61-mrxd[3:0]/ptxd[3:0] 51-mtxc/prxc 52-mtxen/prxdv 57~54-mtxd[3:0]/prxd[3:0] 58-mcol/pcol rxc crs rxdv rxd[3:0] txc txen txd col 4 4 cpu/ processor/ routing engine 44-p4mode[1] 45-p4mode[0] 49-p4lnksta# 47-p4spdsta/p4full 48-p4dupsta/p4spd100 46-p4flctrl/p4enfc pull down floating=high pull down=link on note 1 note 2 note 3 phy mode mii 25mhz 59-mrxc/ptxc 60-mrxdv/ptxen 61-mrxd[0]/ptxd[0] 51-mtxc/prxc 52-mtxen/prxdv 54-mtxd[0]/prxd[0] 58-mcol/pcol 44-p4mode[1] 45-p4mode[0] 49-p4lnksta# 47-p4spdsta/p4full 48-p4dupsta/p4spd100 46-p4flctrl/p4enfc note 1 note 2 note 3 phy mode sni 10mhz pull down rxc crs rxdv rxd txc txen txd col cpu/ processor/ routing engine pull down=link on figure 3. port 4 operating mode overview note 1: pulled high or floating to set speed to 100mbps, and pulled low to set speed to 10mbps. note 2: pulled high or floating to set to full duplex, and pulled low to set to half duplex. note 3: pulled high or floating to enable flow control in full duplex, and pulled low to disable. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 94 track id: jatr-1076-21 rev. 1.2 mac mode mii in homepna or other phy appli cations, the RTL8305SC provides the mii interface to the underlying homepna or other phys ical device in order to communicate with other types of lan media. in such applications, the p4mode[1:0] pins are floating upon reset and the RTL8305SC supports the utp/mii auto-detection function. when both ut p and mii are active (link on), th e utp port has higher priority than the mii port. in homepna applications p4spdsta must be pulled down, as homepn a is half-duplex only. p4dupsta should also be pulled dow n. p4lnksta# must be pulled down instead of being wired to the link led pin of the homepna because of the unstable link state of ho mepna, a characteristic of the homepna 1.0 standard. because the homepna phy physical la yer is half duplex and can only de tect a collision event during the aid header interval (the time when transmitting the et hernet preamble), the back pressure flow control algorithm is not suitable for the homepna networ k and the p4flctrl pin should be pulled down. for other phy applications, p4spdsta, p4dupst a, and p4flctrl depend on the application. 8.1.3. port status configuration the RTL8305SC supports flexible port status co nfiguration for phy by pi n (gxaneg/gyaneg/p4aneg, gxspd100/ gyspd100/p4spd100, and gxfull/gyfull/p4full) on a group basis upon rese t, or by internal registers (reg0.12, reg0.13, reg0.8, and reg4.5/4.6/4.7/4.8) via smi on a pe r-port basis after reset. those pins are used to assign the initial value of mii register 0 and 4 (phy registers) upon reset. the registers can be updated via smi on a pe r-port basis after reset. for exampl e, the initial va lue of register 0.12 of port 4 will be 0 when pin p4aneg is 1 upon reset. all ports support 100base-fx, which shares pins with utp (tx+-/rx+-) and needs no sd+- pins (realtek patent). 100base-fx can be forced into ha lf or full duplex mode w ith optional flow control ability. in order to operate correctly, both sides of the connection should be se t to the same settings. in 100base-fx, duplex and flow control ability can be se t via strapped pins upon reset, or via smi after reset. note: in compliance with ieee 802.3u, 100base-fx does not support auto-negotiation. pins gxaneg/gyaneg/p4aneg as well as gxs pd100/gyspd100/p4spd100 are not used for 100base-fx mode and can be left floating while in 100base-fx mode. for example, port 4 will be forced into full duplex 100base-fx with flow c ontrol ability when p4mode[1:0 ]=10, p4full=1, p4enfc=1 upon reset (regardless of p4spd100 and p4aneg). www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 95 track id: jatr-1076-21 rev. 1.2 when auto-negotiation ability is enabled in ut p mode, the RTL8305SC supports auto-negotiation and parallel detection of 10base-t/10 0base-tx to automatically determine line speed, duplex, and flow control. the parallel detection process is used when connecting a device that does not support auto- negotiation. for example: port0 is utp with all abilities (default for normal switch applications: gxmode=1, gxaneg=1, gxspd100=1, gxfull=1, gxenfc=1. the content of mii regist ers will be reg0.12=1, reg4.5=1, reg4.6=1, reg4.7=1, reg4.8=1, and reg4.10=1). if the connecting device supports auto- negotiation, 10full with 802.3x flow c ontrol ability, port0 w ill enter the auto-neg otiation process. the result will be 10full with 802.3x flow control ability for both devices. if the other device is 10m without auto-negotiation, port0 will enter the parallel de tection process. the result will be 10half without 802.3x flow control ability for port0. note: each port can operate at 10 mbps or 100mbps in full-duplex or half-duplex mode independently of others when auto-negotiation is on. the port status for the phy on a group basis can easily be set by pin configuration. for example, when group x is 100fx (gxmode=0), group x can be set as force mode half duplex by setting pin gxfull to 0. group y can also be set as utp mode nway m ode 10full by setting gymode=1, gyaneg=1, gyspd100=0, gyfull=1. refer to section 5 pin descriptions for details. 8.1.4. flow control the RTL8305SC supports ieee 802.3x full duplex flow cont rol, force mode full d uplex flow control, and optional half duplex back pressure. ieee 802.3x full duplex flow control for utp with auto-negotiation abil ity (gxaneg/gyaneg/p4aneg set to 1), the pause ability (reg.4.10) of full duplex flow control is enabled by pins gx enfc/gyenfc/p4enfc on a group basis upon reset, or internal registers via smi on a pe r-port basis after reset. for ut p with auto-negotiation ability, ieee 802.3x flow control?s ability is auto-negotiated between the re mote device and the RTL8305SC. if the auto-negotiation resu lt of the 802.3x pause ability is ?enabl ed? (reg.4.10=1 and reg.5.10=1), the full duplex 802.3x flow control function is enabled. otherw ise, the full duplex 802.3x flow control function is disabled. force mode full duplex flow control for utp without auto-negotiation ability (g xaneg/gyaneg/p4aneg is 0) and 100base-fx, ieee 802.3x flow control?s ability can be forced to ?enabled? by pins gxenfc/gyenfc/p4enfc on a group basis upon reset, or internal registers (re g.5.10) via smi on a per-port basis after reset. for www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 96 track id: jatr-1076-21 rev. 1.2 example, port 4 will be forced to 10full utp with forced mode full duplex flow control ability, regardless of the connected device, when p4mode[1:0]=10, p4aneg=0, p4spd100=0, p4full=1, p4enfc=1. port 0 will be forced to 100full fx w ith forced mode full duplex flow control ability, regardless of the connected device, when setgroup=1, gxmode=0, gxfull=1, gxenfc=1. regardless of ieee 802.3x full duplex flow control or force mode full duplex flow control, when full duplex flow control is enabled, the RTL8305SC will only recognize the 802.3x flow control pause on/off frames with da=0180c2000001, type = 8808, op -code=01, pause time = maximum to zero, and with a good crc. if a pause frame is received from any pause flow control enabled po rt set to da=0180c2000001, the corresponding port of the RTL8305SC will stop its pack et transmission until the pause timer times out or another pause frame with zero pause time is received. the RTL8305SC will not forward any 802.3x pause frames received from any port. half duplex back pressure if pin endefer is 1, the RTL8305SC will send a preamble to defer the ot her station?s transmission when there is no packet to send. otherwise, if pin ende fer is 0, the RTL8305SC will force a collision with the other station?s transmission when the buffer is full. if pin 48pass1 is 0, the RTL8305SC will always collide with jam (continuous col lision). otherwise, if pin 48pass1 is 1, the RTL8305SC will tr y to forward one packet successf ully after 48 forced collisions (48pass1), to avoid the connected repeater be ing partitioned due to excessive collisions. nway mode for utp with auto-negotia tion ability, pins gxenfc/gyenfc/p4enfc are effective onl y in full duplex mode. therefore, for utp in half duplex mode, half duplex back pressure flow control is controlled by the enbkprs pin strap upon hardware reset. force mode for utp without auto-negotiation ab ility, or in 100base-fx mode, the operation mode can be forced to half duplex. half duplex back pressure flow control can be forced to ?enabled? on the RTL8305SC side by pin gxenfc/gyenfc/p4enfc on a group basis upon reset. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 97 track id: jatr-1076-21 rev. 1.2 8.1.5. address search, learning, and aging when a packet is received, the RTL8305SC will use th e least 10 bits of the de stination mac address to index the 1024-entry lookup table, and at the same time will compare the destination mac address with the contents of the 16-entry cam. if the indexed en try is valid, or the cam comparison is matched, the received packet will be forwarded to the corresp onding destination port. othe rwise, the RTL8305SC will broadcast the packet. this is the ?address search?. the RTL8305SC then extracts the least 10 bits of the source mac address to index the 1024-entry lookup table. if the entry is not already in the ta ble it will record the source mac address and add switching information. if this is an occupied entry, it will update the en try with new information. this is called ?learning?. if the indexed location has been o ccupied by a different mac address (hash collision), the new source mac address will be recorded into the 16-entry cam. the 16-entry cam reduces address hash collisions and improves switching performance. address aging is used to keep the contents of th e address table correct in a dynamic network topology. the lookup engine will update the time stamp informa tion of an entry whenever the corresponding source mac address appears. an entry will be invalid (aged out) if its time stamp information is not refreshed by the address learning process during the aging time period. the aging time of the RTL8305SC is between 200 and 300 seconds. 8.1.6. address direct mapping mode the RTL8305SC uses the least 10 bits of the ma c address to index the 1024-entry lookup table. for example: the index of mac address ?12 34 56 78 90 ab? will be 0xab. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 98 track id: jatr-1076-21 rev. 1.2 8.1.7. half duplex operation in half duplex mode, the csma/cd media access met hod is the means by which two or more stations share a common transmission medium. to transmit, a station waits (defers) fo r a quiet period on the medium (that is, no other station is transmitting) and then sends the intended message in bit-serial form. if the message collides with that of another station, then each transmitting station intentionally transmits for an additional predefined period to ensure propagati on of the collision throughout the system. the station remains silent for a random amount of time (b ackoff) before attempting to transmit again. when a transmission attempt has terminated due to a collision, it is retried until it is successful. a controlled randomization process called ?truncated binary exponential ba ckoff? determines the scheduling of the retransmissions. at the end of enforcing a co llision (jamming), the switch delays before attempting to retransmit the frame. the delay is an integer multip le of slottime (512 bit times). the number of slot times to delay before the n th retransmission attempt is chosen as a uniformly distributed random integer ?r? in the range: 0 r < 2 k where: k = min (n, backofflimit). ieee 802.3 defines the backofflimit as 10. 8.1.8. interframe gap the interframe gap is 9.6s for 10mbps ethe rnet and 960ns for 100mbps fast ethernet. 8.1.9. illegal frame illegal frames such as crc error packets, runt pack ets (length < 64 bytes), and oversize packets (length > maximum length), will be discarded. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 99 track id: jatr-1076-21 rev. 1.2 8.1.10. dual mii interface home gateways, broadband access r outers, and soho routers genera lly contain a powerful network processor, with many i/o interfaces, including mii and sni interfaces. traditionally, this system connects one of the mii interfaces to a single phy as the wan port, and anothe r interface connects to a multi-port switch as the lan ports. in order to meet application demands, realtek offers an advanced dual mii interface for this application. this eliminates the need for a single phy. figure 4 shows the traditional design of a soho router. in this case, the router needs an extra single phy as the wan port. a traditional 5-port switch has five mac and five phy circuits on a single chip. when port 4 is configured as mii-mac/mii-phy/sni-p hy, we only use the mac part of port 4. p0 mac p1 mac p2 mac p3 mac p4 mac p0 phy p1 phy p2 phy p3 phy p4 phy p4_mii lan wan 5 port switch switch core cpu with dual mii mii_1 mii_2 single phy figure 4. traditional application www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 100 track id: jatr-1076-21 rev. 1.2 the RTL8305SC has pin 42, disdualmii, to suppor t both port 4 phy and mac circuits. when the dual mii feature is enabled, the port 4 phy may be used as the wan interface as shown in figure 5. p0 mac p1 mac p2 mac p3 mac p4 mac p0 phy p1 phy p2 phy p3 phy p4 phy p4_mii p2_mii lan wan RTL8305SC switch core cpu with dual mii mii_1 mii_2 figure 5. dual mii application diagram dual mii interfaces configuration port 4 of the RTL8305SC is able to separate the mac and phy circu its via the disdualmii configuration. when disdualmii is configured as 0, the port 4 mac circuit supports mac mode mii, phy mode mii, or phy mode sni interface. the port 4 phy circuit supports an mii on the mac side, and a utp or fiber interface in the p hy transceiver. four pins define the mode of the dual mii interface, disdualmii (pin-42), p4mode[0] (pin-45), p4m ode[1] (pin-44), and p4 phy_mode (pin-68). ? disdualmii: enable dual mii in terface feature, pull high = disa ble, and pull low = enable. ? p4mode[1:0]: when disdualmii is enabled: 11b/10b = p4mac is mac mode mii 01b = p4mac is phy mode mii 00b = p4mac is phy mode sni ? p4phy_mode: when disdualmii is enabled: 1b = p4phy is utp mode 0b = p4phy is fiber mode the following figures show the four types of conf iguration for the RTL8305SC with a cpu application. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 101 track id: jatr-1076-21 rev. 1.2 59-mrxc/ptxc 60-mrxdv/ptxen 67~66, 63~61-mrxd[3:0]/ptxd[3:0] 51-mtxc/prxc 52-mtxen/prxdv 57~54-mtxd[3:0]/prxd[3:0] 58-mcol/pcol mac1_rxc mac1_crs mac1_rxdv mac1_rxd[3:0] mac1_txc mac1_txen mac1_txd[3:0] mac1_col RTL8305SC mac2_rxc mac2_crs mca2_rxdv mac2_rxd[3:0] mac2_txc mac2_txen mac2_txd[3:0] mac2_col 10k ohm 82-phy2txc 83phy2txen 88, 86~84-phy2txd[3:0] 81-phy2rxc 80-phy2rxdv 78~76, 73-phy2rxd[3:0] 89-phy2col 46-p4flctrl user defined 48-p4dupsta user defined 47-p4spdsta user defined 49-p4lnksta# 42-disdualmii 10k ohm 44-p4mode[1] 45-p4mode[0] floating=high 4 4 4 4 mac mode mii interface phy mode mii interface phy mode mii interface mac mode mii interface floating=high cpu/ processor/ routing engine 68- p4phy_mode floating=high figure 6. dual mii mode with 1 mii-mac + 1 mii- phy (100base-t utp) interfaces application circuit 59-mrxc/ptxc 60-mrxdv/ptxen 67~66, 63~61-mrxd[3:0]/ptxd[3:0] 51-mtxc/prxc 52-mtxen/prxdv 57~54-mtxd[3:0]/prxd[3:0] 58-mcol/pcol RTL8305SC mac2_rxc mac2_crs mca2_rxdv mac2_rxd[3:0] mac2_txc mac2_txen mac2_txd[3:0] mac2_col 10k ohm 82-phy2txc 83-phy2txen 88, 86~84-phy2txd[3:0] 81-phy2rxc 80-phy2rxdv 78~76, 73-phy2rxd[3:0] 89-phy2col 46-p4flctrl/p4enfc 48-p4dupsta/p4spd100 47-p4spdsta/p4full user defined 49-p4lnksta# 42-disdualmii 10k ohm 44-p4mode[1] 45-p4mode[0] 4 4 4 4 mac mode mii interface phy mode mii interface of 100base-fx mode phy mode mii interface mac mode mii interface irrelevant mac1_rxc mac1_crs mac1_rxdv mac1_rxd[3:0] mac1_txc mac1_txen mac1_txd[3:0] mac1_col cpu/ processor/ routing engine user defined user defined irrelevant 10k ohm 68- p4phy_mode figure 7. dual mii mode with 1 mii-mac + 1 mii- phy (100base-fx mode) interfaces application circuit www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 102 track id: jatr-1076-21 rev. 1.2 59-mrxc/ptxc 60-mrxdv/ptxen 67~66, 63~61-mrxd[3:0]/ptxd[3:0] 51-mtxc/prxc 52-mtxen/prxdv 57~54-mtxd[3:0]/prxd[3:0] 58-mcol/pcol RTL8305SC mac2_rxc mac2_crs mca2_rxdv mac2_rxd[3:0] mac2_txc mac2_txen mac2_txd[3:0] mac2_col 10k ohm 82-phy2txc 83-phy2txen 88, 86~84-phy2txd[3:0] 81-phy2rxc 80-phy2rxdv 78~76, 73-phy2rxd[3:0] 89-phy2col 46-p4flctrl 48-p4dupsta 47-p4spdsta user defined 49-p4lnksta# 42-disdualmii 10k ohm 44-p4mode[1] 10k ohm 45-p4mode[0] floating=high phy mode mii interface 1 phy mode mii interface 2 4 4 4 4 mac mode mii interface 1 mac mode mii interface 2 mac1_rxc mac1_crs mac1_rxdv mac1_rxd[3:0] mac1_txc mac1_txen mac1_txd[3:0] mac1_col cpu/ processor/ routing engine user defined user defined 68- p4phy_mode floating=high figure 8. dual mii mode with 1 mii-phy + 1 mii-phy (100base-t utp) interfaces application circuit 59-mrxc/ptxc 60-mrxdv/ptxen 61-mrxd[0]/ptxd[0] 51-mtxc/prxc 52-mtxen/prxdv 54-mtxd[0]/prxd[0] 58-mcol/pcol RTL8305SC mac2_rxc mac2_crs mca2_rxdv mac2_rxd[3:0] mac2_txc mac2_txen mac2_txd[3:0] mac2_col 82-phy2txc 83-phy2txen 88, 86~84-phy2txd[3:0] 81-phy2rxc 80-phy2rxdv 78~76, 73-phy2rxd[3:0] 89-phy2col 4 4 phy mode sni interface phy mode mii interface mac mode sni interface mac mode mii interface 10k ohm 46-p4flctrl 48-p4dupsta user defined 47-p4spdsta 49-p4lnksta# 42-disdualmii 10k ohm 10k ohm mac1_rxc mac1_crs mac1_rxdv mac1_rxd mac1_txc mac1_txen mac1_txd mac1_col 44-p4mode[1] 10k ohm 10k ohm 45-p4mode[0] cpu/ processor/ routing engine user defined 68- p4phy_mode floating=high figure 9. dual mii mode with 1 sni-phy + 1 mii- phy (100base-t utp) interfaces application circuit www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 103 track id: jatr-1076-21 rev. 1.2 dual mii registers definition for RTL8305SC single mii interface applications (disdualmii=1), p hy 5 mii registers represent the port 4 mac part. for RTL8305SC dual mii inte rface applications (disdualmii=0), p hy4 registers represent the port 4 phy part (read/write), and phy5 registers re present the port 4 mac part (reg.013, 0.12, 0.8, 4.10, 4.8~4.5 are read/write; others are read-only) . the 100base-fx mode of the phy circuit (p4mode[1:0]=10) only supports 100mbps and full duplex. the phy circui t of utp mode only supports full ability nway (flow control en abled, both 10/100mbps, both full/half duplex). the RTL8305SC support four status pins to provide the link status or initial configuration for the mac circuit. a brief description of the function follows: ? p4lnksta#: determines the link stat us of port 4 mac in real-time ? p4spdsta: provides initial configura tion pin for speed ability upon reset ? p4dupsta: provides initial configurat ion pin for duplex ability upon reset ? p4flctrl: provides initial configuration pin for flow control ability upon reset table 143 shows the mii phy registers of phy4 and phy5 definitions when p4mode[1:0] and disdualmii are configured in various combinations. table 143. mii register definition for phy 4 and phy 5 dis dualmii p4mode [1:0] port 4 mode phy4 (single mode mii) (reg0, 1, 2, 3, 4, 5) phy5 (reg0, 1, 2, 3, 4, 5) port 4 led 1 11 p4lnksta#=1 or p4lnksta#=0 but utp link on: utp upon reset: reg. 0.13=p4spdsta reg. 0.12=p4aneg reg. 0.8=p4dupsta reg. 1.2=signal detection and latch low reg. 4.10=p4flctrl reg. 4.8~4.5= reg. 4.8~4.5 p4 spdsta p4 dupsta 1111 1 1 0111 1 0 0011 0 1 0001 0 0 reg. 5.10=nway result reg. 5.8~5.5=nway result after reset: all rw pins should be fully configurable and act as standard. n/a utp www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 104 track id: jatr-1076-21 rev. 1.2 dis dualmii p4mode [1:0] port 4 mode phy4 (single mode mii) (reg0, 1, 2, 3, 4, 5) phy5 (reg0, 1, 2, 3, 4, 5) port 4 led p4lnksta#=0 and utp link off: mac: mac mode mii phy: n/a utp: n/a n/a upon reset: reg. 0.13=p4spdsta reg. 0.12=p4aneg reg. 0.8=p4dupsta reg. 1.2=p4lnksta# reg. 4.10=p4flctrl reg. 5.10=p4flctrl reg. 4.8~4.5=reg. 5.8~5.5= reg. 4.8~4.5 p4 spdsta p4 dupsta 1111 1 1 0111 1 0 0011 0 1 0001 0 0 after reset: reg. 0.13=configurable reg. 0.12=configurable reg. 0.8=configurable reg. 1.2=p4lnksta# reg. 4.10 and 4.8~4.5= configurable reg. 5.10 and 5.8~5.5=keep the contents identical to reg. 4.10 and 4.8~4.5. port 4 mac 1 10 mac: n/a phy: n/a utp: 100base-fx (fiber) upon reset: reg. 0.13=1 (speed=100m) reg. 0.12=0 (nway=disable) reg. 0.8=p4dupsta reg. 1.2=signal detection reg. 4.10=p4flctrl reg. 4.8~4.5=1111 reg. 5.10=reg. 4.10 reg. 5.8~5.5= reg. 4.8~4.5 after reset: reg. 0.13=1 (speed=100m) reg. 0.12=0 (nway=disable) reg. 0.8=configurable reg. 1.2=signal detection reg. 4.10=configurable reg. 4.8~4.5=1111 reg. 5.10=reg. 4.10 reg. 5.8~5.5=reg. 4.8~4.5 n/a fiber www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 105 track id: jatr-1076-21 rev. 1.2 dis dualmii p4mode [1:0] port 4 mode phy4 (single mode mii) (reg0, 1, 2, 3, 4, 5) phy5 (reg0, 1, 2, 3, 4, 5) port 4 led 1 01 mac: phy mode mii phy: n/a utp: n/a n/a upon reset: reg. 0.13=p4spdsta reg. 0.12=p4aneg reg. 0.8=p4dupsta reg. 1.2=p4lnksta# reg. 4.10=p4flctrl reg. 5.10=p4flctrl reg. 4.8~4.5=reg. 5.8~5.5= reg. 4.8~4.5 p4 spdsta p4 dupsta 1111 1 1 0111 1 0 0011 0 1 0001 0 0 after reset: reg. 0.13=configurable reg. 0.12=configurable reg. 0.8=configurable reg. 1.2=p4lnksta# reg. 4.10 and 4.8~4.5= configurable reg. 5.10 and 5.8~5.5= keep the contents identical to reg. 4.10 and 4.8~4.5. port 4 mac www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 106 track id: jatr-1076-21 rev. 1.2 dis dualmii p4mode [1:0] port 4 mode phy4 (single mode mii) (reg0, 1, 2, 3, 4, 5) phy5 (reg0, 1, 2, 3, 4, 5) port 4 led 1 00 mac: phy mode sni phy: n/a utp: n/a n/a upon reset: reg. 0.13=p4spdsta reg. 0.12=p4aneg reg. 0.8=p4dupsta reg. 1.2=p4lnksta# reg. 4.10=p4flctrl reg. 5.10=p4flctrl reg. 4.8~4.5=reg. 5.8~5.5= reg. 4.8~4.5 p4 spdsta p4 dupsta 1111 1 1 0111 1 0 0011 0 1 0001 0 0 after reset: reg. 0.13=configurable reg. 0.12=configurable reg. 0.8=configurable reg. 1.2=p4lnksta# reg. 4.10 and 4.8~4.5= configurable reg. 5.10 and 5.8~5.5= keep the contents identical to reg. 4.10 and 4.8~4.5. port 4 mac www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 107 track id: jatr-1076-21 rev. 1.2 dis dualmii p4mode [1:0] port 4 mode phy4 (single mode mii) (reg0, 1, 2, 3, 4, 5) phy5 (reg0, 1, 2, 3, 4, 5) port 4 led 0 11 p4phy_mode (pin 68)=1 mac: mac mode mii phy: phy mode mii utp: 100base-tx upon reset: reg. 0.13=1 (speed=100m) reg. 0.12=1 (nway=enable) reg. 0.8=1 (duplex=full) reg. 1.2=signal detection and latch low reg. 4.10=1 (enable fctrl) reg. 4.8~4.5=1111 reg. 5.10=depends on nway result reg. 5.8~5.5=depends on nway result after reset: all rw pins should be fully configurable and act as standard. upon reset: reg. 0.13=p4spdsta reg. 0.12=p4aneg reg. 0.8=p4dupsta reg. 1.2=p4lnksta# reg. 4.10=p4flctrl reg. 5.10=p4flctrl reg. 4.8~4.5=reg. 5.8~5.5= reg. 4.8~4.5 p4 spdsta p4 dupsta 1111 1 1 0111 1 0 0011 0 1 0001 0 0 after reset: reg. 0.13=configurable reg. 0.12=configurable reg. 0.8=configurable reg. 1.2=p4lnksta# reg. 4.10 and 4.8~4.5= configurable reg. 5.10 and 5.8~5.5=keep the contents identical to reg. 4.10 and 4.8~4.5 port 4 phy www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 108 track id: jatr-1076-21 rev. 1.2 dis dualmii p4mode [1:0] port 4 mode phy4 (single mode mii) (reg0, 1, 2, 3, 4, 5) phy5 (reg0, 1, 2, 3, 4, 5) port 4 led 0 10 p4phy_mode (pin 68)=0 mac: mac mode mii phy: phy mode mii utp: 100base-fx (fiber) upon reset: reg. 0.13=1 (speed=100m) reg. 0.12=0 (nway=disable) reg. 0.8=1 (duplex=full) reg. 1.2=signal detection and latch low reg. 4.10=1 (enable fctrl) reg. 4.8~4.5=1111 reg. 5.10=1 reg. 5.8~5.5=1111 after reset: reg. 0.13=1 (speed=100m) reg. 0.12=0 (nway=disable) reg. 0.8=configurable reg. 1.2=signal detection reg. 4.10=configurable reg. 4.8~4.5=1111 reg. 5.10=reg. 4.10 reg. 5.8~5.5=1111 upon reset: reg. 0.13=p4spdsta reg. 0.12=p4aneg reg. 0.8=p4dupsta reg. 1.2=p4lnksta# reg. 4.10=p4flctrl reg. 5.10=p4flctrl reg. 4.8~4.5=reg. 5.8~5.5= reg. 4.8~4.5 p4 spdsta p4 dupsta 1111 1 1 0111 1 0 0011 0 1 0001 0 0 after reset: reg. 0.13=configurable reg. 0.12=configurable reg. 0.8=configurable reg. 1.2=p4lnksta# reg. 4.10 and 4.8~4.5= configurable reg. 5.10 and 5.8~5.5=keep the contents identical to reg. 4.10 and 4.8~4.5 fiber www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 109 track id: jatr-1076-21 rev. 1.2 dis dualmii p4mode [1:0] port 4 mode phy4 (single mode mii) (reg0, 1, 2, 3, 4, 5) phy5 (reg0, 1, 2, 3, 4, 5) port 4 led 0 01 mac: phy mode mii phy: phy mode mii utp: 100base-tx upon reset: reg. 0.13=1 (speed=100m) reg. 0.12=1 (nway=enable) reg. 0.8=1 (duplex=full) reg. 1.2=signal detection and latch low reg. 4.10=1 (enable fctrl) reg. 4.8~4.5=1111 reg. 5.10=depends on nway result reg. 5.8~5.5=depends on nway result after reset: all rw pins should be fully configurable and act as standard. upon reset: reg. 0.13=p4spdsta reg. 0.12=p4aneg reg. 0.8=p4dupsta reg. 1.2=p4lnksta# reg. 4.10=p4flctrl reg. 5.10=p4flctrl reg. 4.8~4.5=reg. 5.8~5.5= reg. 4.8~4.5 p4 spdsta p4 dupsta 1111 1 1 0111 1 0 0011 0 1 0001 0 0 after reset: reg. 0.13=configurable reg. 0.12=configurable reg. 0.8=configurable reg. 1.2=p4lnksta# reg. 4.10 and 4.8~4.5= configurable reg. 5.10 and 5.8~5.5=keep the contents identical to reg. 4.10 and 4.8~4.5 port 4 phy www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 110 track id: jatr-1076-21 rev. 1.2 dis dualmii p4mode [1:0] port 4 mode phy4 (single mode mii) (reg0, 1, 2, 3, 4, 5) phy5 (reg0, 1, 2, 3, 4, 5) port 4 led 0 00 mac: phy mode sni phy: phy mode mii utp: 100base-tx upon reset: reg. 0.13=1 (speed=100m) reg. 0.12=1 (nway=enable) reg. 0.8=1 (duplex=full) reg. 1.2=signal detection and latch low reg. 4.10=1 (enable fctrl) reg. 4.8~4.5=1111 reg. 5.10=depends on nway result reg. 5.8~5.5=depends on nway result after reset: all rw pins should be fully configurable and act as standard. upon reset: reg. 0.13=p4spdsta reg. 0.12=p4aneg reg. 0.8=p4dupsta reg. 1.2=p4lnksta# reg. 4.10=p4flctrl reg. 5.10=p4flctrl reg. 4.8~4.5=reg. 5.8~5.5= reg. 4.8~4.5 p4 spdsta p4 dupsta 1111 1 1 0111 1 0 0011 0 1 0001 0 0 after reset: reg. 0.13=configurable reg. 0.12=configurable reg. 0.8=configurable reg. 1.2=p4lnksta# reg. 4.10 and 4.8~4.5= configurable reg. 5.10 and 5.8~5.5=keep the contents identical to reg. 4.10 and 4.8~4.5 port 4 phy 8.2. physical layer functional overview 8.2.1. auto-negotiation for utp the RTL8305SC obtains the states of duplex, speed, and flow control ability for each port in utp mode through the auto-negotiation mechanism defined in the ieee 802.3u specifi cations. during auto- negotiation, each port advertises its ability to its link partner and compar es its ability with advertisements received from its link partner. by default, the r tl8305sc advertises full capab ilities (100full, 100half, 10full, 10half) together w ith flow control ability. 8.2.2. 10base-t transmit function the output 10base-t waveform is manchester-encoded be fore it is driven into the network media. the internal filter shapes the driven signals to reduce emi emissions, eliminating the need for an external filter. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 111 track id: jatr-1076-21 rev. 1.2 8.2.3. 10base-t receive function the manchester decoder converts the incoming serial stream to nrz data when the squelch circuit detects the signal level is above squelch level. 8.2.4. link monitor the 10base-t link pulse detection ci rcuit continually monitors the rxip/rxin pins for the presence of valid link pulses. auto-polarity is implemented to correct the detected reve rse polarity of rxip/rxin signal pairs. 8.2.5. 100base-tx transmit function the 100base-tx transmit function performs parallel to serial conversion, 4b/5b coding, scrambling, nrz/nrzi conversion, and mlt-3 enc oding. the 5-bit serial data str eam after 4b/5b coding is then scrambled as defined by the tp-pmd stream cipher function to flatten the power spectrum energy such that emi effects can be reduced significantly. the scrambled seed is based on phy addresses and is unique for each port. after scrambling, the bit stream is driven into the network media in the form of mlt-3 signaling. the mlt-3 multi-level signaling technology moves the powe r spectrum energy from high frequency to low frequency, which also reduces emi emissions. 8.2.6. 100base-tx receive function the receive path includes a receiver composed of an adaptive equalizer and dc restoration circuits (to compensate for an incoming distorted mlt-3 signal), an mlt-3 to nrzi and nr zi to nrz converter to convert analog signals to digital bit- stream, and a pll circuit to clock data bits with minimum bit error rate. a de-scrambler, 5b/4b decoder, and serial-to- parallel conversion circu its are followed by the pll circuit. finally, the converted parallel data is fed into the mac. 8.2.7. 100base-fx all ports support 100base-fx, which shares pins with utp (tx+-/rx+-) and needs no sd+- pins. 100base-fx can be forced to half or full duplex with optional flow control ability. note: in compliance with ieee 802.3u, 100base-fx does not support auto-negotiation. in order to operate correctly, both sides of the connection should be set to the same duplex and flow control ability. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 112 track id: jatr-1076-21 rev. 1.2 a scrambler is not needed in 100base-fx. co mpared to common 100base-fx applications, the RTL8305SC removes a pair of differe ntial sd (signal detect) signals that provide a link monitoring function, which reduces the pin count (realtek patent). 8.2.8. 100base-fx transmit function in 100base-fx transmission, di-bits of txd are processed as 100base-tx except without being scrambled before the nrzi stage. instead of convert ing to mlt-3 signals as in 100base-tx, the serial data stream is driven out as nrzi pecl (positive emitter coupled logic) signals, which enter the fiber transceiver in differential-pairs fo rm. the fiber transceiver may be 3.3v or 5v capable. refer to 100base- fx application, on page 143 for an example application. table 144. pecl dc characteristics parameter symbol min max unit pecl input high voltage vih vdd-1.16 vdd-0.88 v pecl input low voltage vil vdd-1.81 vdd-1.47 v pecl output high voltage voh vdd-1.02 v pecl output low voltage vol vdd-1.62 v 8.2.9. 100base-fx receive function signals are received through positive emitter coupl ed logic (pecl) receive r inputs from a fiber transceiver and directly passed to a clock recovery circuit for data/clock recovery. scrambling/de- scrambling is bypassed in 100base-fx. 8.2.10. 100base-fx fefi when 100fx is enabled, phy reg.1.4 (remote fault) is the far-end-fault-indica tor (fefi) bit for ports, and indicates that a fefi has been detected. the fefi is an alternative in-band si gnaling that is composed of 84 consecutive 1?s followed by one 0. when the r tl8305sc has detected this pattern three times, reg.1.4 will be set, which means the transmit path (r emote side?s receive path) has problems. on the other hand, to send an fefi stream pattern, the follo wing condition needs to be satisfied; the incoming signal causes link failure, which in turn causes the remote side to detect a far-end-fault. this means that the receive path has a problem from the view of the RTL8305SC. the fefi mechanism is used only in 100base-fx. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 113 track id: jatr-1076-21 rev. 1.2 during detection of the fefi, phy re g.1.4 should be set to 1. it should rema in 1, even after it is read, as long as fefi is continuously de tected by the RTL8305SC. phy reg.1.4 should not be cleared until the fefi has disappeared. if there is no fefi, then phy reg.1.4 should be 0. in normal conditi ons where there is no optical or electrical input sign al; opt-phy should not detect far-end-fault signals since th ere is no such signal at the optical input. when optical receiving fiber is disconnected from RTL8305SC, the fefi cannot be detected by the RTL8305SC and also cannot be reflected on phy reg.1.4 since there is no fefi. if there is a fefi before optical receiving fiber is disconnected, reg.1.4 should be kept on 1. this bit should be cleared to 0 after it is read (read and clear). the opt-phy of RTL8305SC will not reflect the fefi (reg.1.4=1) when optical fiber is disconnected at power up, in spite of no-far-end-fault signals. after power on, the default value of phy reg1.4 will appear as ?0?. 8.2.11. reduced fiber interface the RTL8305SC ignores the underlying sd signal of the fiber transceiver to comp lete link detection and connection. this is achieved by monitoring rd signals from the fiber transcei ver and checking whether any link integrity events are met. this significantly reduces pin-count, especially for high-port phy devices. this is a realtek patent -pending technology and available on ly with realtek product solutions. 8.2.12. power saving mode the RTL8305SC implements power saving mode on a pe r-port basis. a port automatically enters power saving mode 10 seconds after the cable is disconnected from it. once a po rt enters power saving mode, it transmits normal link pulses only on its txop/txon pins and continue s to monitor the rxip/rxin pins to detect incoming signals, which might be the 100bas e-tx mlt-3 idle pattern, 10base-t link pulses, or auto-negotiation?s flp (fast link pulse). after it de tects any incoming signals, it wakes up from power saving mode and operates in normal mode according to the result of the connection. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 114 track id: jatr-1076-21 rev. 1.2 8.2.13. reg0.11 power-down mode the RTL8305SC implements power-down mode on a per-port basis. setti ng mii reg.0.11 forces the corresponding port of the RTL8305SC to enter power-down mode. this disables all transmit/receive functions, except smi (serial management interf ace: mdc/mdio, also known as mii management interface). 8.2.14. crossover detection and auto correction during the link setup phase, the RTL8305SC checks wh ether it receives active signals on every port in order to determine if a connection can be established. in cases where the receiver data pin pair is connected to the transmitter data pi n pair of the peer device and vice versa, the RTL8305SC automatically changes its configuration and swaps receiver/transmitter data pins as required. if a port is connected to a pc or nic with mdi-x interface with a crossover cable, the rtl 8305sc will reconfigure the port to ensure proper connection. this re places the dip switch commonly used for reconfiguri ng a port on a hub or switch. by pulling-up en_autoxover, the RTL8305SC identifi es the type of connected cable and sets the port to mdi or mdix. when switching to mdi mode , the RTL8305SC uses txop/n as transmit pairs; when switching to mdix mode, the RTL8305SC uses rxip/n as transm it pairs. this function is port- based. pulling-down en_autoxover disables this function, the RTL8305SC operates in mdi mode, in which txop/n represents transmit pairs, and rxip/n represents receive pairs. ieee 802.3 compliant forced mode 100m ports with autoxover have link issues with nway (auto- negotiation) ports. it is recommended to not use autoxover for forced 100m. 8.2.15. polarity detection and correction for better noise immunity and lower interference to ambient devices, the ethern et electrical signal on a twisted pair cable is transmitted in differential form. that is, the signal is transmitted on two wires in each direction with inverse polarities (+/- ). if wiring on the connector is faulty or a faulty transformer is used, the two inputs to a transceiver may carry signals w ith opposite but incorrect polarities. as a direct consequence, the transceive r will not work properly. when the RTL8305SC operates in 10base-t mode, it au tomatically reverses the polarity of its two receiver input pins if it detects that the polarities of the incoming signals on the pins is incorrect. however, this feature is unnecessary when the RTL8305SC is operating in 100base-tx mode. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 115 track id: jatr-1076-21 rev. 1.2 8.3. advanced functional overview 8.3.1. reset the whole or just part of the RTL8305SC is initialized depending on the reset type. there are several ways to reset the RTL8305SC: hardware reset for the whole chip by pin reset#, soft reset for all except phy by register softreset, and phy softwa re reset for each phy by register reset. hardware reset : pin reset#=0 set to reset#=1 (for at least 1ms). the RTL8305SC resets the whole chip and then gets initial values from pins and serial eeprom. soft reset : write bit12 of reg16 of phy0 as 1. the r tl8305sc resets all except phy and does not load eeprom and pin registers with serial eep rom and pins. the softreset, eeprom, and pin registers are designed to provide a convenient way for users who wa nt to use smi to change the configuration. after changing the ee prom or pin registers via smi (s erial management interface), the external device has to perform a soft re set in order to update the configuration. phy software reset : write bit15 of reg0 of a phy as 1. the RTL8305SC will then reset this phy. hardware reset soft reset: after loading eeprom completely, the user may access eeprom/pin registers via smi. a soft reset to reset all except phy is required to update pin/eeprom configuration. strap pin upon reset load eeprom upon reset figure 10. reset some setting values for operation m odes are latched from those corresponding mode pins upon hardware reset. ?upon reset? is defined as a short time af ter the end of a hardware reset. other advanced configuration parameters may be latched from serial eeprom if pin eneeprom=1. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 116 track id: jatr-1076-21 rev. 1.2 8.3.2. setup and configuration the RTL8305SC can be configured easily and flexib ly by hardware pins upon reset, optional serial eeprom upon reset, and internal registers (includi ng phy registers for each port and mac register for global) via smi (serial management interface: mdc/mdio, also known as mii management interface). there are three methods of configuration: 1. only hardware pins for normal switch applications 2. hardware pins and serial eeprom for advanced switch applications 3. hardware pins and internal registers via smi for applications with processor three types of pins, each with internal pull-hi gh resistors, are used for configuration: 1. input pins used for strappi ng upon reset (unused after reset) 2. input/output pins (mtxd[3:2] /prxd[3:2]/p4irtag[1:0], mtxd[1:0]/prxd[1:0]/ledmode[1:0]) used for strapping upon reset and us ed as output pins after reset 3. input/output pins (all leds) used for strapping upon re set and used as led indi cator pins after reset. the led statuses are represented as active-low or high depending on input st rapping, except bi-color link/act in bi-color led mode, whose polarity de pends on spd status pins with default value=1 are intern al pull-high and use i/o pads. they can be left floa ting to set input value as high, but should not be connect ed to gnd without a pull-down resistor. the serial eeprom shares two pins, scl_mdc and sda_mdio, w ith smi, and is optional for advanced configuration. scl_mdc and sda_mdio are tri-state during hardware reset (pin reset#=0). the RTL8305SC will try to automatically find the serial eeprom upon reset only if pin eneeprom=1. if the first byte of the serial eeprom is not 0xff (noeeprom bit of the first byte=0), the RTL8305SC will load all contents of the serial eeprom into internal registers. otherwise, the RTL8305SC will use the default internal values. internal registers can still be accessed after reset via smi (pin scl_mdc and sda_mdio). serial eeprom signals and smi signals must not exist at the same time. in order to use the smi to flexibly change configuration, internal regist ers include the contents of some pins and all serial eeprom. these registers do not work in real ti me and a soft reset is necessary after changing the eeprom or pin registers. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 117 track id: jatr-1076-21 rev. 1.2 8.3.3. serial eeprom example: 24lc02 the 24lc02 interface is a 2- wire serial eeprom interface providing 2k bits of storage space. the 24lc02 must be 3.3v compatible. 8.3.3.1 24lc02 device operation clock and data transitions: the sda pin is normally pulled high with an external resistor. data on the sda pin may change only during scl low time peri ods. data changes during scl high periods will indicate a start or stop c ondition as defined below. start condition: a high-to-low transition of sd a with scl high is the start condition and must precede any other command. stop condition: a low-to-high transition of sda w ith scl high is a stop condition. acknowledge: all addresses and data are transmitted serially to and from the eeprom in 8-bit words. the 24lc02 sends a zero to acknowledge that it has received each word. this happens during the ninth clock cycle. random read: a random read requires a ?dummy? byte write se quence to load in the data word address. sequential read: for the RTL8305SC, the sequential reads ar e initiated by a random address read. after the 24lc02 receives a data word, it responds with an acknowledgement. as long as the 24lc02 receives an acknowledgement, it will continue to increment th e data word address and clock out sequential data words in series. sda scl start stop figure 11. start and stop definition scl data in data out start acknowledge 1 89 figure 12. output acknowledge www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 118 track id: jatr-1076-21 rev. 1.2 sda device address dummy write word address n device address data n stop ack ack ack no ack r/w start start write read figure 13. random read sda device address stop no ack data n+x data n+1 data n ack r/w read ack ack ack ack figure 14. sequential read www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 119 track id: jatr-1076-21 rev. 1.2 8.3.4. smi the smi (serial management interface) is also known as the mii manage ment interface, and consists of two signals (mdio and mdc). it allows external de vices with smi master mode (mdc is output) to control the state of the phy and in ternal registers (smi slave mode: mdc is input). mdc is an input clock for the RTL8305SC to latch mdio on its risi ng edge. the clock can ru n from dc to 25mhz. mdio is a bi-directional connection used to write data to, or read data from the RTL8305SC. the phy address is from 0 to 4. table 145. smi read/write cycles preamble (32 bits) start (2 bits) op code (2 bits) phyad (5 bits) regad (5 bits) turn around (2 bits) data (16 bits) idle read 1??..1 01 10 a 4 a 3 a 2 a 1 a 0 r 4 r 3 r 2 r 1 r 0 z0 d 15 ??.d 0 z* write 1??..1 01 01 a 4 a 3 a 2 a 1 a 0 r 4 r 3 r 2 r 1 r 0 10 d 15 ??.d 0 z* note: z*: high-impedance. during idle time mdio state is determined by an external 1.5k ? pull-up resistor. the RTL8305SC supports preamble suppression, which allows the mac to issue read/write cycles without preamble bits. however, fo r the first cycle of mii manageme nt after power-on reset, a 32-bit preamble is needed. to guarantee the first successful sm i transaction after power-on reset, the external device should delay at least 1second before issuing the first smi read/write cycle relative to the rising edge of reset. 8.3.5. head-of-line blocking the RTL8305SC incorporates an advanced mechanis m to prevent head-of-line blocking problems when flow control is disabled. when the flow control function is disabled, the RTL8305SC first checks the destination address of the incoming packet. if th e destination port is conge sted, the RTL8305SC will discard this packet to avoid bl ocking the next packet, which is going to a non-congested port. 8.3.6. port-based vlan if the vlan function is enab led by pulling down the strapping pi n disvlan, the default vlan membership configuration by internal register is port 4 overlapped with all the other ports to form four individual vlans. this default configuration of the i nput port could be modified via an attached serial eeprom or smi interface. the 16 vlan membership registers designed into the RTL8305SC provide full flexibility for users to configure the input ports to associate with different vlan groups. each input port can join more than one vlan group. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 120 track id: jatr-1076-21 rev. 1.2 port-based vlan mapping is the simplest implicit ma pping rule. each ingress pa cket is assigned to a vlan group based on the input port. it is not necessa ry to parse and inspect frames in real-time to determine their vlan association. all the packets re ceived on a given input port will be forwarded to this port?s vlan members. the RTL8305SC supports five vlan indexe s for each port to individually index this port to one of the 16 vlan membership registers. these 16 vlan membership registers, vlan id [a] membership bit [4:0] ~ vlan id [p] membership bit [4:0] , describe which ports are the members of this vlan. the RTL8305SC forwards packets to the members of this vlan only (excluding the input port of this frame). a port that is not included in a vlan?s member set cannot transmit packets to this vlan. figure 15 illustrates a typical appl ication. vlan indexes and vlan member definitions are set to form three different vlan groups. vlan 1 vlan 2 port 0 vlan index=0000 port 1 vlan index=0000 port 4 vlan index=0001 port 3 vlan index=0001 port 2 vlan index=0000 RTL8305SC p0 p1 p2 p3 p4 membership [a] 0 0 1 1 1 membership [c] 0 0 0 0 0 membership [b] 1 1 0 0 0 membership [p] 0 0 0 0 0 figure 15. vlan grouping example for port-based vlan configuration, each ingress port is allotted an index register to index to this port?s ?port vlan membership? register, which can be defi ned in one of the registers from ?vlan id [a] membership bit [4:0]? to ?vlan id [p] membership bit [4:0]? register. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 121 track id: jatr-1076-21 rev. 1.2 using the default value as an example: ? port 0 vlan index[3:0]=2?b0000 means th e member set of port 0 is defined in the ?vlan id [a] membership? register ? port 1 vlan index[3:0]=2?b0001 means th e member set of port 0 is defined in the ?vlan id [b] membership? register ? port 2 vlan index[3:0]=2?b0010 means th e member set of port 0 is defined in the ?vlan id [c] membership? register ? port 3 vlan index[3:0]=2?b0011 means th e member set of port 0 is defined in the ?vlan id [a] membership? register ? port 4 vlan index[3:0]=2?b0100 means th e member set of port 0 is defined in the ?vlan id [a] membership? register for non-vlan tagged frames, the RTL8305SC performs port-based vlan. it will use ?port n vlan index [3:0]? register to index to a vlan membership. the vlan id associated with this indexed vlan membership is the port vid (pvid) of this port. 8.3.7. ieee 802.1q tagged-vid based vlan the RTL8305SC supports 16 vlan entries to perf orm 802.1q tagged-vid ba sed vlan mapping. in 802.1q vlan mapping, the RTL8305SC uses a 12-bit explic it identifier in the vlan tag to associate received packets with a vlan . the 16 groups of vlan membersh ip registers, ?vlan id [a] membership [4:0] ~ vlan id [p] membership [4:0]?, consist of the ports that are in the same vlan corresponding to the registers defined in register ?v lan id [a] [11:0] ~ vlan id [p] [11:0]?. if the vid of a vlan-tagged frame does not hit any one of th e registers in ?vlan id [a] [11:0] ~ vlan id [p] [11:0]?, the RTL8305SC will perform port-ba sed vlan mapping to the member set indexed by register ?port n vlan index [3:0]? . otherwise, the RTL8305SC compares the explicit identifier in the vlan tag with the 16 vlan id regist ers to determine the vlan association of this packet, and then forwards this packet to the member set of this vl an. two vids are reserved for special purposes. one of them is all 1?s, which is reserved and currently unused. the other is all 0?s, which indicates a priority tag. a priority-tagged frame should be treated as an untagged frame. when ?802.1q tag aware vlan? at phy0 reg.16.10 is enabled, the RTL8305SC performs 802.1q tag- based vlan mapping for tagged frames, but still performs port-based vl an mapping for untagged frames. if ?802.1q tag aware vlan? is disable d, the RTL8305SC performs only port-based vlan mapping both on non-tagged and tagged frames. figure 16 illustrates the processi ng flow when ?802.1q tag aware vlan? is disabled. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 122 track id: jatr-1076-21 rev. 1.2 p0vlanindex=0000 vid [p]=0x00f RTL8305SC tagged vid [c]=0x002 vid [b]=0x001 vid [a]=0x000 search vid table p0 p1 p2 p3 p4 un-tagged membership [a] 1 0 0 0 1 membership [c] 1 0 1 0 0 membership [b] 1 0 0 1 0 membership [i] 1 0 0 0 1 ------ da sa 802.1q tag length/ type ------ da sa length/ type ------ da sa 802.1q tag length/ type ------ da sa length/ type figure 16. tagged and untagged packet forwarding when 802.1q tag aware vlan is disabled two vlan ingress filtering function s are supported by the RTL8305SC in registers. one is the ?vlan tag admit control? defined in phy0 reg.16.8, which pr ovides the ability to receive vlan-tagged frames only. untagged or priority tagged (vid=0) frames will be dropped. the othe r is ?vlan member set ingress filtering? defined in p hy0 reg.16.9, which will drop frames if the receive port is not in the member set. there are also two optional egress filtering func tions supported by the RTL8305SC through strapping. one is ?leaky vlan? at phy0 reg18.11, which e . that is, if the layer 2 lookup table search has a hit, then the unicast packet will be forwarded to the egre ss port, ignoring the egress rule. the other is ?arp vlan? at phy0 reg.18.10, which will broadcast arp pack ets to all other ports, ignoring the egress rule. 8.3.8. port vid (pvid) in a router application, the rout er may want to know which input port this packet came from. the RTL8305SC supports port vid (pvid) for each port to insert a pvid in the vlan tag on an egress packet. the vid information carried in the vlan ta g will be changed to a pvid. the RTL8305SC also provides an option to admit vlan tagged packets with a specific pv id only. when this function is enabled, packets with an incorrect pvid , and non-tagged packets will be dropped. the RTL8305SC uses an internal register, port n vlan index [3:0,] to index to one of the 16 vlan entries. the vlan id associated with this indexe d vlan entry is the pvid for this port. users may select vlan insert/remove type 10 or 00 to insert a pvid on egress packets. in 802.1q tag-based vlan applications, do not use a port-based vlan pvid applications as the vid information carried in the vlan ta g will be replaced with a pvid. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 123 track id: jatr-1076-21 rev. 1.2 8.3.9. lookup table access the RTL8305SC supports registers for the cpu to read or write an internal 1 024-entry lookup table via the smi interface. before reading/writing from/to the in ternal forwarding table, th e contents of internal register, indirect access contro l [15:0] at phy4 register 16, should be filled correctly. in the write cycle, the user must assign the write da ta in register indirect access data 0, 1, 2, and 3 at phy4 register 17~20 first. register 17, bits [1:0] al ong with bits [15:8] form a 10-bit field (entry index [9:0]), which is indirectly mapped to an entry in th e lookup table. to execute write access, bit 0 in the indirect access control register shou ld be set to 0, and bit 1 should be set to 1. the cpu will poll bit 1 in indirect access control to determine whet her the write access is complete on not. in the read cycle, the user only has to enter the read addre ss of the lookup table in re gister indirect access data 0, 1, 2, and 3 at phy4 register 17~20 first. register 17, bits [1:0 ] along with bits [15:8] form a 10-bit field (entry index [9 :0]). to execute read access, bit 0 in the indirect access control register should be set to 1, and bit 1 should be set to 1 to tr igger this command. the cpu will poll bit 1 in indirect access control to determine whether read access is complete or not. 8.3.10. qos function the RTL8305SC can recognize the qos priority information of incomi ng packets to give a different egress service priority. the RTL8305SC identifies the packets as hi gh priority based on several types of qos priority information: ? port-based priority ? 802.1p/q vlan priority tag ? tcp/ip?s tos/diffserv (ds) priority field there are two priority queues; a hi gh-priority queue, and a low-priority queue. the queue service rate is based on the weighted round robin algorithm, the packet -based service weight ra tio of the high-priority queue and low-priority queue can be set to 4:1, 8:1, 16: 1 or ?always high priority first? by hardware pins upon reset, or internal regi ster via smi after reset. port-based priority when port-based priority is applie d, packets received from the high-prio rity port are sent to the high- priority queue of the destination port. high priority ports can be pa rtially set by hardware pins, and wholly configured by registers. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 124 track id: jatr-1076-21 rev. 1.2 802.1p-based priority when 802.1p vlan tag priority is enabled, the RTL8305SC recognize s the 802.1q vlan tag frames and extracts the 3-bit user priority information from the vlan tag. the RTL8305SC default sets the threshold of user priority as 4. therefore, vlan tagged frames with user priority value = 4~7 will be treated as high priority frames, and user priority values=0~3 will be treated as low priority frames (follows the ieee 802.1p standard). the threshold value can be modified in internal registers via an smi interface or configured in eeprom. diffserv-based priority when tcp/ip?s tos/diffserv(ds) based priority is enabled, the rtl 8305sc recognizes tcp/ip differentiated services codepoint (dscp) priority information from the ds-field defined in rfc 2474. the ds field byte in ipv4 is a type-of-service (t os) octet. the recommended diffserv codepoint is defined in rfc 2597 to classify the traffic into different service cl asses. the RTL8305SC extracts the codepoint value of ds-fields from ipv4 packets, and identifies the priority of the incoming ip packet according to the following definition: high priority: where the ds-field = (ef, expected forwarding:) 101110 or (af, assured forwarding:) 001010; 010010; 011010; 100010 or (network control:) 110000 and 111000. low priority: where the ds-field = other values. the vlan-tagged frame and 6-bit ds-field in the ipv4 frame format are shown below: table 146. 802.1q vlan tag frame format 6 bytes 6 bytes 2 bytes 3 bits da sa 81-00 user-priority (0~3: low-pri; 4~7: high-pri) ---- table 147. ipv4 frame format 6 bytes 6 bytes 4 bytes 2 bytes 4 bits 4 bits 6 bits da sa 802.1q tag (optional) 08-00 version ipv4= 0100 ihl tos[0:5]= ds- field ---- www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 125 track id: jatr-1076-21 rev. 1.2 8.3.11. insert/remove vlan tag the RTL8305SC supports four types of insert/remove vlan packet tags, controlled by inte rnal registers on a per-port basis. they are classified as follows: type 11: do not change packets (default). type 10: insert input port?s vlan tags for non-tagged packets. do not change packets if they are already tagged. type 01: remove vlan tags from tagged packets. do not change packets if they are not tagged. type 00: remove vlan tags from tagged packets, th en insert the input port?s vlan tags. for non- tagged packets, insert the input port?s vlan tags. if a tagged frame is less than 64 bytes after remova l of the tag, it will be pa dded with an 0x20 pattern before the packet?s crc field to fit the 64-byte minimum packet length of the ieee 802.3 spec. the RTL8305SC will recalculate the fc s (frame check sequence) if the frame has been changed. 8.3.12. filtering/forwarding reserved control frame the RTL8305SC supports the ability to forward or drop the frames of the ieee 802.1d specified reserved multicast addresses. table 148. reserved multicast address address function control bit control bit=0 control bit=1 01-80-c2-00-00-00 bridge group address n/a broadcast 01-80-c2-00-00-01 pause control frame n/a drop 01-80-c2-00-00-03 ieee802.1x control frame n/a broadcast 01-80-c2-00-00-02 and 01-80-c2-00-00-04 to 01-80-c2-00-00-0f reserved enforward drop *broadcast any other multicast address - n/a broadcast note: * indicates the default setting. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 126 track id: jatr-1076-21 rev. 1.2 8.3.13. broadcast storm control according to the latched value of the disbrdctrl pin upon reset, the RTL8305SC determines whether or not to proceed with broadcast storm control. once enabled (disbrdctrl=0), after 64 consecutive broadcast packets (did=ff-ff-ff-ff- ff-ff) are received by a particular port, this port will discard following incoming broadcast packets for approximately 800ms. any non-broadcas t packet can reset the time window and broadcast counter such that the scheme restarts. note: trigger condition: consecutive 64 did = ff- ff-ff-ff-ff-ff packets. release condition: receive non-broadcast packet on or after 800ms. 8.3.14. broadcast in/out drop if some destination ports are bloc king and the buffer is full, broadc ast frames are dropped according to configuration. 1. input drop: do not forward to any port and drop the frame directly 2. output drop: forward only to non-bloc king ports (broadcast becomes multicast) port 0 1 2 3 4 rx: full input drop 1. broadcast packet from port0 2. buffer of port4 is full, others are not full rx: full output drop port 0 1 2 3 4 figure 17. input drop vs. output drop www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 127 track id: jatr-1076-21 rev. 1.2 8.3.15. loop detection loops should be avoided between sw itch applications. the simplest lo op as shown below results in: 1) unicast frame duplication; 2) broadcast frame multiplication; 3) address table non-convergence. frames may be transmitted from swit ch1 to switch 2 via link 1, then returned to switch 1 via link 2. switch 1 link 1 switch 2 link 2 figure 18. loop example when the loop detection function is enabled, the RTL8305SC periodical ly sends out a broadcast 64-byte packet every 3~5 minutes and automa tically detects whether there is a network loop (or bridge loop). if a loop is detected, the loopled# will be on (activ e low or high). the led goes out when both RTL8305SC ports of the loop are unpl ugged. the loop frame length is 64 bytes and its format is shown below. table 149. loop frame format ffff ffff ffff sid 8899 0300 000?0000 crc in order to achieve loop detecti on, each switch device needs a unique si d (the source mac address). if the eeprom is not used, a unique si d should be assigned via smi afte r reset, and the default sid (52- 54-4c-83-05-c0) shou ld not be used. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 128 track id: jatr-1076-21 rev. 1.2 8.3.16. mac local loopback return to external each port supports loopback of the mac (return to external device) for diagnostic purposes. example 1: if the internal register, phy4 re g.22.13=0 (local loopback), the RTL8305SC will forward local and broadcast packets from the input of port 4 to the output of port 4, and drop unicast packets from the input of port 4. other ports can still forward br oadcast or unicast packets to port 4. example 2: if the internal register, phy3 reg. 22.13=0 (local loopback), the RTL8305SC will ?forward local and broadcast packets from the input of port3 to the output of port3? and ?drop unicast packets from the input of port3?. other ports can still forward broadcast or unicast packets to port3. this is especially useful for ro uter applications performing mass production tests. this function is independent of phy type (gxmode/gymode/p4mode[1 :0]) and can be done on each mode. below are two examples: in example 1 the external device (cpu) is connected to the mii or sni interface of port 4. in example 2, the external device (cpu) does not have an mii or sni interface, so it uses the pci interface to connect an rtl8139 to the utp port of port 4. cpu utp example 2: loopback in utp mode rtl8139 pci RTL8305SC example 1: loopback in external phy mode RTL8305SC cpu mii/sni figure 19. port 4 loopback www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 129 track id: jatr-1076-21 rev. 1.2 8.3.17. reg.0.14 phy digital lo opback return to internal the digital loopback mode of the phy (return to in ternal mac) may be enabled on a per-port basis by setting mii reg.0.14 to 1. in digital loopback mode, the txd of phy is transferred direc tly to the rxd of phy with txen changed to crs_dv, and returns to mac via an internal mii. the data stream coming from the mac will not egress to the physical medium, and an incoming data stream from the network medium will be blocked in this mode. the p ackets will be looped back in 10mbps full duplex or 100mbps full duplex mode. this functi on is especially useful for dia gnostic purposes. for example, a nic can be used to send broadcast frames into port0 of the RTL8305SC and set port1 to reg0.14 loopback. the frame will be looped back to port 0, so the received packet count can be checked to verify that the switch device is good. in this example, port0 can be 10m or 100m and full or half duplex. mac phy internal mii figure 20. reg. 0.14 loopback as the RTL8305SC only supports digital loopback in full duplex mode, phy reg.0.8 for each port will always be kept on 1 when digital loopback is enab led. the digital loopback only functions on broadcast packets (da=ff-ff-ff-ff-ff-ff). in loopback mode, th e link led of the loopback port should always be on, and the speed and duplex led combined to reflect the link status (100full/10full) correctly, regardless of what the previous st atus of this loopback port was. consider a case where a port is initially unlinked. when we set this port to digital loopback mode, the RTL8305SC can get this port linked up within 100ms at the c onfigured speed, and wi ll block the sending of utp or fiber signals from this port. 8.3.18. leds the RTL8305SC supports four parallel leds for each port, and two special leds (selmiimac# and loopled#). each port has four led indicator pins. each pin may have different indicator meanings set by pins ledmode[1:0]. refer to the pin descriptions for details (port led pins, on page 20). upon reset, the RTL8305SC supports chip diagnostics and led f unctions by blinking all leds once for 320ms. this function can be disabled by asserting en_rst_l ink to 0. led_blink_time determines the led blinking period for activity and collision (1=43ms and 0=120ms). the parallel leds corresponding to www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 130 track id: jatr-1076-21 rev. 1.2 port 4 can be tri-stated (disab le led functions) for mii port a pplication by setting enp4led in eeprom to 0. in utp applications, this bit should be set to 1. all led pins are dual function pins: input operati on for configuration upon re set, and output operation for led after reset. if th e pin input is floating upon reset, the pi n output is active low after reset. otherwise, if the pin input is pulled down upon reset, the pin output is active high after reset. exception: bi-color link/act mode of pin led_add[4:0] when ledmode[1:0]=10. below is an example circuit for leds. the typical values for pu ll-down resistors are 10k ? . led pin pull down 10k ohm 330 ohm RTL8305SC RTL8305SC led pin floating 330 ohm 3.3v figure 21. floating and pull-down of led pins for two-pin bi-color led mode ( ledmode[1:0]=10), bi-color link/a ct (pin led_add) and spd (pin led_spd) can be used for one bi-color led package, which is a single led package with two leds connected in parallel wi th opposite polarity. when ledmode[1:0]= 10, the active status of led_add is the opposite of led_spd. table 150. spd and bi-color link/act truth table spd: input=floating, active low. bi-color link/act: the active status of led_add is the opposite of led_spd and does not interact with input upon reset. spd: input=pull-down, active high. bi-color link/act: the active status of led_add is the opposite of led_spd and does not interact with input upon reset. indication bi-color state spd link/act spd link/act no link both off 1 1 0 0 100m link green on 0 1 1 0 10m link yellow on 1 0 0 1 100m act green flash 0 flash 1 flash 10m act yellow flash 1 flash 0 flash www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 131 track id: jatr-1076-21 rev. 1.2 yellow green led_spd led_add figure 22. two pin bi-color led for spd floating or pull-high yellow green l ed _spd led_add figure 23. two pin bi-color led for spd pull-down www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 132 track id: jatr-1076-21 rev. 1.2 8.3.19. 1.8v power generation the RTL8305SC can use a pnp transistor to genera te 1.8v from a 3.3v power supply. this 1.8v is used for the digital core and analog receiver circuits. do not use one pnp transistor for more than one RTL8305SC chip, even if the rating is enough. us e one transistor for each RTL8305SC chip. do not connect an inductor (bead) di rectly between the collector of the pnp transistor and avdd18. this will adversely affect the stability of the 1.8v power to a significant degree. RTL8305SC vctrl dvdd33 avdd18 hvdd33, dvdd33: 3.3v dvdd18, avdd18: 1.8v 1.8v 47uf/10uf/0.1uf 2sb1188 ic(max.) = 2a dvdd18 bead 0 ? 3.3v hvdd33 bead 1n4001 diode figure 24. using a pnp transistor to transform 3.3v into 1.8v table 151. an example using power transistor 2sb1188 parameter symbol limits unit collector-base voltage vcbo -40 v collector-emitter voltage vceo -32 v emitter-base voltage vebo -5 v collector current ic -2 a(dc) collector power dissipation pc 0.5 w junction temperature tj 150 c storage temperature tstg -55~+150 c note: absolute maximum ratings (ta=25 c). for more information, refer to http://www.rohm.com 8.3.20. crystal/oscillator the frequency is 25mhz. the maxi mum frequency tolerance is +/-50ppm. the maximum jitter is 150ps peak-to-peak. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 133 track id: jatr-1076-21 rev. 1.2 9. characteristics 9.1. absolute maximum ratings warning: absolute maximum ratings are limits beyond wh ich permanent damage may be caused to the device, or device reliability will be affected. all voltages are specified reference to gnd unless otherwise specified. table 152. electrical characteristics/ratings parameter min max units vcc supply referenced to gnd -0.5 +4.0 v digital input voltage -0.5 vdd v dc output voltage -0.5 vdd v 9.2. operating range parameter min max units storage temperature -55 +150 c ambient operating temperature (ta) 0 +70 c 3.3v vcc supply voltage range (hvdd33, dvdd33) 3.15 3.45 v 1.8v vcc supply voltage range (dvdd18, avdd18) 1.71 1.95 v www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 134 track id: jatr-1076-21 rev. 1.2 9.3. dc characteristics parameter sym condition min typical max units power supply current for 1.8v icc 10base-t, idle 10base-t, peak continuous 100% utilization 100base-tx, idle 100base-tx, peak continuous 100% utilization power saving power down 40 500 460 470 40 40 45 525 470 480 45 45 50 550 480 490 50 50 ma power supply current for 3.3v icc 10base-t, idle 10base-t, peak continuous 100% utilization 100base-tx, idle 100base-tx, peak continuous 100% utilization power saving power down 110 100 110 100 60 60 120 110 120 110 65 65 130 120 130 120 70 70 ma total power consumption for all ports ps 10base-t, idle 10base-t, peak continuous 100% utilization 100base-tx, idle 100base-tx, peak continuous 100% utilization power saving power down 295 1230 1191 1176 270 270 477 1308 1242 1227 295.5 295.5 519 1386 1293 1278 321 321 mw ttl input high voltage v ih 2.0 v ttl input low voltage v il 0.8 v ttl input current i in -10 10 ua ttl input capacitance c in 3 pf output high voltage v oh 2.25 v output low voltage v ol 0.4 v output three state leakage current | i oz | 10 ua www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 135 track id: jatr-1076-21 rev. 1.2 9.4. ac characteristics parameter sym condition min typical max units transmitter, 100base-tx differential output voltage, peak-to-peak v od 50 ? from each output to vcc, best-fit over 14 bit times 1.007 v differential output voltage symmetry v os 50 ? from each output to vcc, | vp+ | / | vp- | 99.1 % differential output overshoot v oo percent of vp+ or vp- 3.1 % rise/fall time t r ,t f 10-90% of vp+ or vp- 4.1 ns rise/fall time imbalance | t r - t f | 0.17 ns duty cycle distortion deviation from best-fit time-grid, 010101 ? sequence 0.2 ns timing jitter idle pattern 0.87 ns td differential output impedance (return loss) return loss margin from 2hz to 80mhz for reference resistance of 100 ? . the margin is the minimum difference between the limit line and the return loss curve 4.6 db rd differential output impedance (return loss) return loss margin from 2hz to 80mhz for reference resistance of 100 ? . the margin is the minimum difference between the limit line and the return loss curve 4.6 db transmitter, 10base-t differential output voltage, peak-to-peak v od 50 ? from each output to vcc, all pattern 2.36 v tp_idl silence duration period of time from start of tp_idl to link pulses or period of time between link pulses 10.48 ms td short circuit fault tolerance peak output current on td short circuit for 10 seconds. 24 ma td common-mode output voltage ecm terminate each end with 50 ? resistive load 43.2 mv transmitter output jitter 6 ns harmonic content db below fundamental, 20 cycles of all ones data 28 db start-of-idle pulse width tp_idl width 256 ns www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 136 track id: jatr-1076-21 rev. 1.2 9.5. digital timing characteristics table 153. led timing parameter sym condition min typical max units led timing led on time tledon while led blinking 43 120 ms led off time tledoff while led blinking 43 120 ms t h t s mrxc/ptxc, phy2ptxc, mdc mrxd/ptxd[3: 0], phy2ptxd[3: 0], mrxdv/ptxen, phy2ptxen, mcol, phy2pcol, mdio figure 25. reception data timi ng of mii/sni/smi interface t cyc t os mtxc/prxc, phy2prxc, mdc mtxd/prxd[3:0], phy2prxd[3:0], mtxen/prxdv, phy2prxdv, pcol, phy2pcol, mdio t oh figure 26. transmission data timing of mii/sni/smi interface www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 137 track id: jatr-1076-21 rev. 1.2 table 154. mii & smi dc timing parameter sym condition i/o min type max units mac mode mii timing 100baset mtxc/mrxc, mrxc/ptxc t cyc mtxc/mrxc, mrxc/ptxc clock cycle time i 40 50 ppm ns 10baset mtxc/mrxc, mrxc/ptxc t cyc mtxc/mrxc, mrxc/ptxc clock cycle time i 400 50 ppm ns mtxd[3:0]/prxd[3:0], mtxen/prxdv output setup time t os output setup time from mtxc/prxc rising edge to mtxd[3:0]/prxd[3:0], mtxen/prxdv o 34 34.8 36 ns mtxd[3:0]/prxd[3:0], mtxen/prxdv output hold time t oh output hold time from mtxc/prxc rising edge to mtxd[3:0]/prxd[3:0], mtxen/prxdv o 4 5.2 6 ns mrxd[3:0]/ptxd[3:0], mrxdv/ptxen, mcol/pcol setup time t s mrxd[3:0]/ptxd[3:0], mrxdv/ptxen to mrxc/ptxc rising edge setup time i 4 ns mrxd/ptxd, mrxdv/ptxen, mcol/pcol hold time t h mrxd[3:0]/ptxd[3:0], mrxdv/ptxen to mrxc/ptxc rising edge hold time i 2 ns phy mode mii timing 100baset mtxc/mrxc, mrxc/ptxc, phy2ptxc, phy2prxc t cyc mtxc/mrxc, mrxc/ptxc, phy2ptxc, phy2prxc clock cycle time o 40 50 ppm ns 10baset mtxc/prxc, mrxc/ptxc, phy2ptxc, phy2prxc t cyc mtxc/mrxc, mrxc/ptxc, phy2ptxc, phy2prxc clock cycle time o 400 50 ppm ns mtxd/prxd[3:0], phy2prxd[3:0], mtxen/prxdv, phy2prxdv mcol/pcol, phy2pcol output setup time t os output setup time from mtxc/prxc rising edge to mtxd[3:0]/prxd[3:0], phy2prxd[3:0], mtxen/prxdv, phy2prxdv mcol/pcol, phy2pcol o 17.2 18.2 19.2 ns mtxd/prxd[3:0], phy2prxd[3:0], mtxen/prxdv, phy2prxdv mcol/pcol, phy2pcol output hold time t oh output hold time from mtxc/prxc rising edge to mtxd[3:0]/prxd[3:0], phy2prxd[3:0], mtxen/prxdv, phy2prxdv mcol/pcol, phy2pcol o 20.8 21.8 22.8 ns mrxd/ptxd[3:0], phy2ptxd[3:0], mrxdv/ptxen, phy2ptxen setup time t s mrxd[3:0]/ptxd[3:0], mrxdv/ptxen to mrxc/ptxc rising edge setup time i 4 ns mrxd/ptxd[3:0], phy2ptxd[3:0], mrxdv/ptxen, phy2ptxen hold time t h mrxd[3:0]/ptxd[3:0], mrxdv/ptxen to mrxc/ptxc rising edge hold time i 2 ns www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 138 track id: jatr-1076-21 rev. 1.2 parameter sym condition i/o min type max units phy mode sni timing mtxc/mrxc, mrxc/ptxc t cyc mtxc/prxc, mrxc/ptxc clock cycle time o 100 50 ppm ns mtxd/prxd[0], mtxen/prxdv, mcol/pcol output setup time t os output setup time from mtxc/prxc rising edge to mtxd[0]/prxd[0], mtxen/prxdv, mcol/pcol o 36 38 40 ns mtxd/prxd[0], mtxen/prxdv, mcol/pcol output hold time t oh output hold time from mtxc/prxc rising edge to mtxd[0]/prxd[0], mtxen/prxdv, mcol/pcol o 59 60 61 ns mrxd/ptxd[0], mrxdv/ptxen setup time t s mrxd[0]/ptxd[0], mrxdv/ptxen to mrxc/ptxc rising edge setup time i 4 ns mtxd/prxd[0], mtxen/prxdv, mcol/pcol hold time t h mtxd[0]/prxd[0], mrxdv/ptxen to mrxc/ptxc rising edge hold time i 2 ns smi timing mdc t cyc mdc clock cycle i 40 ns mdio setup time t s write cycle i 10 ns mdio hold time t h write cycle i 10 ns mdio output delay relative to rising edge of mdc t ov read cycle o 10 s www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 139 track id: jatr-1076-21 rev. 1.2 9.6. thermal characteristics 9.6.1. package description table 155. package description item parameter type qfp128 device RTL8305SC dimension (l x w) 14 x 20 mm thickness 2.85 mm 9.6.2. pcb description table 156. pcb description item parameter dimension (l x w) 50 x 70 mm number of cu layer 2 layers (80% of cu trace coverage of top/bottom layer) 9.6.3. assembly material table 157. assembly material item material thermal conductivity k (w/m-k) die silicon 147 lead frame c7025 168 silver paste ag03*7 2.0 mold compound 6300hg 0.63 fr4 0.21 pcb cu 393 www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 140 track id: jatr-1076-21 rev. 1.2 9.6.4. simulation analysis conditions table 158. simulation analysis conditions item parameter air flow rate 0, 1, 2, 3 m/s control condition power=1.386 w ambient temperature 60 c 9.6.5. results table 159. results air flow (m/s) 0 1 2 3 tj ( c) 117.3 112.1 109.6 108.2 tc ( c) 111.0 104.7 101.8 100.2 ja ( c/w) 41.3 37.6 35.8 34.8 jt ( c/w) 4.51 5.33 5.61 5.79 where: tj is the maximum junction temperature. tc is the maximum case temperature. ja is the junction-to-ambient thermal resistance. jc is the junction-to-case thermal resistance. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 141 track id: jatr-1076-21 rev. 1.2 10. application information 10.1. utp (10base-t/100base-tx) application in reviewing this material, please be advised that the center-tap on the primary side of the transformer must be left floating a nd should not be connected to ground through capacitors. table 160. transformer vendors vendor quad single pulse h1164 h1102 magnetic 1 ml164 ml102 two types of transformers are generally used for the RTL8305SC. one is a quad (4 port) transformer with one common pin on both sides for an internal connected central tap. another is a single (1 port) transformer with two pins on both sides for a separate central tap. RTL8305SC 1 4 3 2 5 8 7 6 rxin txop txon ibref rxip transformer rj-45 1:1 1:1 chassis gnd 1.96?, 1% 0.1uf 50pf/2kv 50? 1% 75? 50? 1% 50? 1% 50? 1% agnd agnd 0.1uf agnd 75? 75? agnd 0.1uf 1.8v figure 27. utp application for transformer with connected central tap www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 142 track id: jatr-1076-21 rev. 1.2 RTL8305SC 1 4 3 2 5 8 7 6 rxin txop txon ibref rxip pulse h1102 transformer rj-45 1:1 1:1 chassis gnd 50pf/2kv agnd 0.1uf 75? 75? 75? 75? 1.96?, 1% 1.8v 50? 1% 50? 1% 50? 1% 50? 1% 1.8v 0.1uf agnd agnd figure 28. utp application for transformer with separate central tap www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 143 track id: jatr-1076-21 rev. 1.2 10.2. 100base-fx application the following is an example of an RTL8305SC connecting to a 3.3v fibe r transceiver application circuit with a siemens v23809-c8-c10 (3.3v~5v fiber tran sceiver, 1*9 sc duplex multimode 1300 nm led fast ethernet/fddi/atm op tical transceiver module). 1 gnd_rx 2 rd+ 3 rd- 4 sd 5 vcc_rx 6 vcc_tx 7 td- 8 td+ 9 gnd_tx 100base-fx fiber transceiver chassis gnd rxip rxin txon txop fiber_rx_3v fiber_tx_3v fiber_rx_3.3v fiber_rx_3.3v agnd RTL8305SC 130? 130? 130? 130? 82? 82? 82? 82? agnd agnd agnd figure 29. 100base-fx with 3.3v fiber transceiver application www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 144 track id: jatr-1076-21 rev. 1.2 figure 30 shows an example of an RTL8305SC connected to a 5v fiber transceiver application circuit with a siemens v23809-c8-c10 (3.3v~5v fiber tran sceiver, 1*9 sc duplex multimode 1300nm led fast ethernet/fddi/atm op tical transceiver module). RTL8305SC 1 gnd_rx 2 rd+ 3 rd- 4 sd 5 vcc_rx 6 vcc_tx 7 td- 8 td+ 9 gnd_tx 100base-fx fiber transceiver chassis gnd rxip rxin txon txop 82? 82? 50? 50? 130? 130? 250? 250? fiber_rx_5v fiber_tx_5v fiber_tx_5v fiber_rx_5v 100? 100? 82? 82? figure 30. 100base-fx with 5v fiber transceiver application www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 145 track id: jatr-1076-21 rev. 1.2 11. design and layout guide in order to achieve maximum performance using the RTL8305SC, good design attention is required throughout the design and layout pro cess. the following are some suggestions to implement a high performance system. general guidelines ? provide a good power source, minimizing noise fr om switching power supply circuits (<50mv). ? verify the ability of critical components, e.g. cl ock source and transformer, to meet application requirements. ? keep power and ground noise levels below 50mv. ? use bulk capacitors (4.7f-10f) be tween the power and ground planes. ? use 0.1f de-coupling capacitors to reduce high -frequency noise on the power and ground planes. ? keep de-coupling capacito rs as close as possible to the RTL8305SC chip. differential signal layout guidelines ? keep differential pairs as close as possible a nd route both traces as id entically as possible. ? avoid vias and layer changes if possible. ? keep transmit and receive pair s away from each other. run orthogonal or separate by a ground plane. clock circuit ? if possible, surround the clock by ground tr ace to minimize high-frequency emissions. ? keep the crystal or oscillator as close to the RTL8305SC as possible. 1.8v power ? do not connect a bead directly between the co llector of the pnp transistor and avdd18. this will significantly affect the stab ility of the 1.8v power supply. ? use a bulk capacitor (4.7f-10f) between the collector of the pnp tr ansistor and the ground plane. ? do not use one pnp transistor for more than one RTL8305SC chip, even if the rating is enough. use one transistor for each RTL8305SC chip. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 146 track id: jatr-1076-21 rev. 1.2 power plane ? divide the power plane into 1.8v dig ital, 3.3v digital, and 1.8v analog. ? use 0.1f decoupling capacitors and bulk capac itors between each power plane and the ground plane. ? power line connects from the source to the RTL8305SC pin should be at least 10 mil wide. ground plane ? keep the system ground region as one continuous, unbroken plane that extends from the primary side of the transformer to the rest of the board. ? place a moat (gap) between the system ground and chassis ground. ? ensure the chassis ground area is voided at some point such that no ground loop exists on the chassis ground area. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 147 track id: jatr-1076-21 rev. 1.2 12. mechanical dimensions see detail ?a? see detail ?f? gage plane detail ?a? base metal with plating seating plane detail ?f? see the mechanical dimensions notes on the next page. www.datasheet.co.kr datasheet pdf - http://www..net/ RTL8305SC datasheet 5-port 10/100mbps single-chip dual mii switch controller 148 track id: jatr-1076-21 rev. 1.2 12.1. mechanical dimensions notes symbol dimensions in inches dimensions in mm notes: min typical max min typical max 1. dimensions d & e do not include interlead flash. a - - 0.134 - - 3.40 2. dimension b does not include dambar rotrusion/intrusion. a1 0.004 0.010 0.036 0.10 0.25 0.91 3. controlling dimension: millimeter a2 0.102 0.112 0.122 2.60 2.85 3.10 4. general appearance spec. should be based on final visual b 0.005 0.009 0.013 0.12 0.22 0.32 inspection. c 0.002 0.006 0.010 0.05 0.15 0.25 d 0.541 0.551 0.561 13.75 14 .00 14.25 ti tle: pqfp-128 e 0.778 0.787 0.797 19.75 20.00 20.25 -cu l/f, footprint 3.2 mm e 0.010 0.020 0.030 0.25 0.5 0.75 leadframe material: hd 0.665 0.677 0.689 16.90 17.20 17.50 approve doc. no. he 0.902 0.913 0.925 22.90 23.20 23.50 version 1.2 l 0.027 0.035 0.043 0.68 0.88 1.08 page l1 0.053 0.063 0.073 1.35 1.60 1.85 check dwg no. q128 - 1 y - - 0.004 - - 0.10 date 12 february 2003 0 - 12 0 - 12 realtek semico nductor corp. 13. ordering information table 161. ordering information part number package status RTL8305SC 128-pin pqfp RTL8305SC-lf 128-pin pqfp lead (pb)-free package realtek semiconductor corp. headquarters no. 2, industry east road ix, science-based industrial park, hsinchu, 300, taiwan, r.o.c. tel: 886-3-5780211 fax: 886-3-5776047 www.realtek.com.tw www.datasheet.co.kr datasheet pdf - http://www..net/ |
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